Geoffrey Yeap

Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-/spl Aring/ gate oxide MOSFETs

This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.

Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities

The explosive growth of smart mobile wireless devices in recent years has fundamentally transformed the semiconductor industry. Mobile system-on-chips (SoCs) has become the leading product driver for technology definition and manufacturing for the semiconductor industry. This trend was first observed in 28 nm and will continue for 20 nm, 16/14 nm, and 10 nm adoption and production ramp. Recent mobile SoC performance increase was achieved mainly through silicon technology scaling, and from single to dual- and quad-core. For mobile SoCs to continue offering new and exciting user-experiences, and longer battery life, a holistic approach in orthogonal system scaling to break out of the box of (speed*density/power/cost) constrains is mandated. Examples in the new paradigm of mobile heterogeneous computing are: energy-efficient transistors/memories/interconnects in expanding and boosting existing SoC functionalities (e.g., SiGe/III-V FinFET, GAA-FET, TFET, and RRAM/MRAM etc.), all-inclusive technology/design co-optimization to extract more values from silicon tech, RFFE system integration, and the multi-die integration by system partitioning that allows each component to be optimized and integrated closely together for lower cost and power, higher performance, and reduced form factor. Numerous challenges are ahead yet tremendous opportunities exist for collaborative and multiplicative innovations in the industry to enable the continued growth of mobile SoCs.

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with Tfin = 10 nm and Hfin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.

Read-Preferred SRAM Cell With Write-Assist Circuit Using Back-Gate ETSOI Transistors in 22-nm Technology

The degradation of the read stability and write ability of static random-access memory (SRAM) is becoming a critical problem in deep submicrometer technology. To solve this problem, there are many SRAM cell design options such as preferred cells and assist circuits. In addition, extremely thin silicon-on-insulator (ETSOI) with a buried oxide offers an independent back-gate control. In this paper, previously proposed SRAM back-gate-assist circuit schemes are analyzed. From this, we propose a read-preferred SRAM cell with a write-assist circuit using the back-gate ETSOI. The proposed write-assist circuit minimizes the dynamic power overhead and satisfies a sufficient cell sigma in all cells during the read and write operations.

Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides

Summary form only given. In this paper, we report the performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling (DT) gate oxides. Both pure oxides and nitrided oxides down to 17 /spl Aring/ were investigated. For a L/sub g/ of about 90 nm (L/sub eff/ of about 50 nm), a drive current of larger than 1.0 mA//spl mu/m and a transconductance of higher than 800 mS/mm were obtained at room temperature. Channel electron transport properties were investigated. High field mobility degradation with decrease of oxide thickness and subsequent improvement with use of nitrided oxides were observed. Reliability characteristics such as gate leakage, stress-induced-leakage, and hot-carrier degradation are described. A new mechanical stress induced leakage phenomenon for ultra thin DT oxides was revealed.

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology

Although near-threshold (Vth) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, for static random access memory (SRAM) cells. This brief proposes a near-Vth 9T SRAM cell implemented in a 22-nm FinFET technology. The read buffer of the proposed cell ensures read stability by decoupling the stored node from the read bit-line and improves read performance using a one-transistor read path. Energy and standby power are reduced by eliminating the sub-Vth leakage current in the read buffer. For accurate sensing yield estimation, a new yield-estimation method is also proposed, which considers the dynamic trip voltage. The proposed SRAM cell can achieve a minimum operating voltage of 0.3 V.

Asymmetric Independent-Gate MOSFET SRAM for High Stability

In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array architecture is also suggested to prevent read stability degradation in the half-selected cell, where word line is selected but bit line is unselected. The previous SRAMs with IG-MOSFET (IG-SRAMs) fail to simultaneously improve read stability and writeability compared to the SRAM with the tied-gate MOSFET. The proposed IG-SRAM significantly improves both read stability and writeability at the cost of slightly increased bit-cell area and read delay, as compared to the previous IG-SRAMs.

BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit

POLY gate defined lateral ESD diodes were fabricated, characterized and modeled using Foundry standard 65nm CMOS technology. Compare to conventional STI diode, the lateral diode demonstrated superior Q-factor and TLP IT2 due to the reduced transport distance and RC constant. Aided by BSIM4 MOS transistor model, a physically based scalable lateral diode model was developed and presented here for the first time. The accuracy of the diode model was validated with RF characterization data over a broad device geometrical range. The model was successfully used in LNA and ESD CDM protection co-design. A good match of LNA RF performance between Si-data and model prediction was achieved. Experimental results showed that LNA with Lateral Diode protection passed +/−500V ESD CDM zap voltage, while LNA with STI diode started to fail at only −250V.

Accurate projection of V ccmin by modeling “dual slope” in FinFET based SRAM, and impact of long term reliability on end of life V ccmin

Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40mV increase of Vccmin to meet 99% target yield for 32nm HK/MG planar 1M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1∶2∶2(=PU∶PG∶PD), HD and LD 32M FinFET SRAMs improve Vccmin by 370mV and 500mV, respectively, compared to 32M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.