Mohammad Al-Amin

Increasing minority carrier lifetime in as-grown multicrystalline silicon by low temperature internal gettering

We report a systematic study into the effects of long low temperature (≤500 °C) annealing on the lifetime and interstitial iron distributions in as-grown multicrystalline silicon (mc-Si) from different ingot height positions. Samples are characterised in terms of dislocation density, and lifetime and interstitial iron concentration measurements are made at every stage using a temporary room temperature iodine-ethanol surface passivation scheme. Our measurement procedure allows these properties to be monitored during processing in a pseudo in situ way. Sufficient annealing at 300 °C and 400 °C increases lifetime in all cases studied, and annealing at 500 °C was only found to improve relatively poor wafers from the top and bottom of the block. We demonstrate that lifetime in poor as-grown wafers can be improved substantially by a low cost process in the absence of any bulk passivation which might result from a dielectric surface film. Substantial improvements are found in bottom wafers, for which annealing at 400 °C for 35 h increases lifetime from 5.5 μs to 38.7 μs. The lifetime of top wafers is improved from 12.1 μs to 23.8 μs under the same conditions. A correlation between interstitial iron concentration reduction and lifetime improvement is found in these cases. Surprisingly, although the interstitial iron concentration exceeds the expected solubility values, low temperature annealing seems to result in an initial increase in interstitial iron concentration, and any subsequent decay is a complex process driven not only by diffusion of interstitial iron.

Passivation Effects on Low-Temperature Gettering in Multicrystalline Silicon

Annealing at ≤ 500 °C changes minority carrier lifetime in as-grown multicrystalline silicon substantially. Part of the change arises from internal gettering of impurities, but surface passivation for lifetime measurement results in additional effects. We report experiments that aim to clarify the role of passivation. Long-term annealing (up to 60 h) is performed on silicon nitride passivated multicrystalline silicon, and lifetime and interstitial iron concentrations are monitored at each processing stage. Lifetime in all samples is improved under certain conditions, with improvements always achieved at 400 °C. Increases are pronounced in low-lifetime bottom samples, with improvement by a factor of 2.7 at 400 °C or 3.8 at 500 °C. Important differences are found compared with our previous study with iodine-ethanol passivation. First, as-received lifetime is higher with silicon nitride not due to a substantial difference in surface recombination. Second, while interstitial iron concentrations often initially increase with iodine-ethanol, they tend to reduce with silicon nitride. Third, lifetime in high-lifetime samples reduces substantially with iodine-ethanol but increases with silicon nitride. Secondary ion mass spectrometry reveals high iron concentrations in annealed silicon nitride. Results are discussed in terms of gettering of impurities to, and bulk passivation arising from, silicon nitride films.

Low temperature internal gettering of bulk defects in silicon photovoltaic materials

Multicrystalline silicon (mc-Si) substrates are widely used for photovoltaic cells. The minority carrier lifetime in mc-Si is affected by recombination associated with metallic impurities in many forms, such as point-like defects, precipitates and bound to or precipitated at structural defects such as dislocations. We have studied the effect of low temperature annealing on the lifetime and bulk iron concentration in as-received mc-Si wafers from different locations within a block. Lifetime measurements are made using a temporary iodine-ethanol surface passivation technique to minimize the occurrence of bulk hydrogenation which often occurs from dielectric films. In good wafers from the middle of the block the lifetime is reduced by annealing at 400 °C and 500 °C in a way which does not correlate with changes in bulk iron concentration. Lifetime improvements occur in relatively poor samples from the top and bottom of the block annealed at 300 °C, and also in samples from the bottom annealed at 400 °C. The improvement in bottom wafers correlates with iron loss from the bulk. Our work shows that under some conditions the lifetime in relatively poor as-grown wafers can be improved by low temperature internal gettering.

Combining Low-Temperature Gettering With Phosphorus Diffusion Gettering for Improved Multicrystalline Silicon

We have investigated low-temperature (≤500 °C) gettering in combination with phosphorus diffusion gettering with a view to improving poor quality multicrystalline silicon. Low-temperature gettering applied after standard phosphorus diffusion gettering is found to provide a >40% improvement in minority carrier lifetime in samples from the top and bottom of an ingot. The best results are achieved at 300 °C with very long annealing times (>24 h). Improvements in the lifetime do not correlate with changes in interstitial iron concentration. Experiments are performed to assess whether the presence of a phosphorus-diffused emitter affects low-temperature gettering, and results from sister samples show the low-temperature gettering behavior is not affected by the existence of an emitter. Further experiments show that low-temperature gettering prior to phosphorus diffusion results in a 20% higher lifetime after phosphorus diffusion. Low-temperature gettering can, therefore, enhance lifetime even when used in conjunction with standard phosphorus diffusion gettering.

Hydrogénation effect on low temperature internal gettering in multicrystalline silicon

We have performed a comprehensive study into low temperature (< 500 °C) internal gettering in multicrystalline silicon (mc-Si). Two groups of as-grown mc-Si wafers from different ingot height positions were subjected to the same thermal treatments with surface passivation by either silicon nitride (SiNx:H) or a temporary iodine-ethanol (I-E) chemical solution. With either passivation scheme, lifetime in the relatively low lifetime samples from the bottom of the ingot improves substantially. There are however key passivation-dependent differences in behavior in other parts of the ingot. Lifetime in relatively good wafers from the middle of the ingot is improved significantly with silicon nitride passivation but not with iodine-ethanol, for which substantial reductions in lifetime initially occur. There are also key differences in the internal gettering behavior of bulk iron. We suggest the differences arise because silicon nitride introduces hydrogen into the bulk, whereas the iodine-ethanol does not.

Enhancement of electrical performance of c-Si PV modules through optimized soldering process

Soldering techniques used to interconnect large thin c-Si solar cells in PV modules have a significant impact on the generated electrical power and reliability of the manufactured modules. Poor soldering process results on an abnormal mechanical or thermal stress which leads to micro cracks, cell breakage, and lower adhesion force. Moreover, poor soldering increases the contact resistance (Rc) between the busbar and ribbon and lowers the fill factor (FF) of the PV module. In this paper, the impact of process parameters in an automated induction soldering process has been examined. Different adhesion force (AF) profiles and relationship with current transport mechanism have been investigated. AF is increased with temperature till 240-260°C whereas it is lowered at low and very high soldering temperature. Electroluminescence (EL) image showed that solar cell is prone to micro-cracks at higher temperature but observed as a random event. Modules were processed with different soldering conditions and characterized. Results show that, using the suggested soldering process, FF can be improved by 0.53, and the power output can be as high as 251.26 W, which is higher by 2.50% compared to the non-optimized process.

Reducing the parasitic loss of c-Si solar cells

Parasitic loss in monocrystalline silicon (mc-Si) solar cell significantly degrades the cells electrical performance. However, surface contamination due to the presence of organic residues and non-optimized silicon nitride properties (SiNx), and deposits by plasma- enhanced chemical vapor deposition (PECVD), lead to higher parasitic loss. In this research work, a cleaning process by using sodium hypo chlorate (NaOCl) and potassium hydroxide (KOH) is introduced before the anisotropic texturization by sodium/potassium hydroxide (NaOH/KOH) and Isopropyl alcohol (IPA) solutions. The surface morphology, reflectance factor (RF) are investigated and compared. Furthermore, SiNx layer properties have been optimized and the effect of process parameters on shunt resistance (RSH) has been analyzed. A batch of 156 mm pseudo square (PSQ) mc-Si solar cells are fabricated with the optimized process where electrical properties are analyzed and compared with the standard one. RSH, fill factor (FF) and efficiency are found to be higher by 40%, 1.6% (absolute) and 0.37% (absolute) respectively for the optimized process.

Enhancement of electrical performance of acid textured multi crystalline silicon solar cells

Multicrystalline silicon (mc-Si) material is a promising alternative to monocrystalline CZ silicon because of its lower cost. Solar cell industries are investing in the improvement of electrical performance of mc-Si to make it competitive in the solar cell market. To improve the absorption of incident light, an isotropic texture using nitric acid (HNO3), hydrofluoric acid (HF) and demineralized (i.e. dionized) water (DI H2O) is widely used but leads to etch pits at the grain boundary. In this research work, the formation of etch pits and its impact on the electrical performance of the solar cell has been analyzed. In addition, phosphorus diffusion temperature, phosphorus concentration, coating thickness (CT), refractive index (RI) of the anti reflection coating (ARC), and sintering speed of metal electrodes have been investigated. A batch of 156 mm2(SQ) is fabricated with 16.54% average cell efficiency which is 0.42%absolute higher and the shunt resistance (Rsh) is increased by two fold compared to the standard process. The surface morphology, reflectance factor (RF), open circuit voltage (Voc), short circuit current (Isc), fill factor (FF), and cell efficiency (η) have been analyzed and compared also with the standard process.