Mohammad Faisal Amir

Ultra-low power electronics with Si/Ge tunnel FET

Si/Ge Tunnel FET (TFET) with its subthermal subthreshold swing is attractive for low power analog and digital designs. Greater Ion/Ioff ratio of TFET can reduce the dynamic power in digital designs, while higher gm/IDS can lower the bias power of analog amplifier. However, the above benefits of TFET are eclipsed by MOSFET at a higher power/performance point. Ultra low power scalability of the key analog and digital circuits, SRAM and operational transconductance amplifier (OTA), with TFET is demonstrated. Analyzing a TFET based cellular neural network, this work shows the feasibility of ultra-low-power neuromorphic computing with TFET.

NeuroSensor: A 3D image sensor with integrated neural accelerator

3D integration provides opportunities to design high-bandwidth and low-power CMOS image sensors (CIS) [1–4]. The 3D stacking of pixel tier, peripheral tier, memory tier(s), and compute tier(s) enables high degree of parallel processing. Also, each tier can be designed in different technology nodes (heterogeneous integration) to further improve power-efficiency. This paper presents a case study of a smart 3D image sensor with integrated neuro-inspired computing for intelligent vision processing. Hardware acceleration of neuro-inspired computing has received much attention in recent years for recognition and classification [5]. We present the physical design of NeuroSensor, a 3D CIS with an integrated convolutional neural network (CNN) accelerator. The rationale for our approach is that 3D integration of sensor, memory, and computing will effectively harness the inherent parallelism in neural algorithms. We design the NeuroSensor considering different complexities of CNN platform, ranging from only feature extraction to complete classification, and study the trade-offs between complexity, performance, and power.

Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory

Ultra-low-power embedded memory is emerging as a key challenge to design systems with stringent energy but relaxed performance constraints like various wireless sensors and Internet-of-Things (IoT) devices. This paper explores the potential of Si/Ge tunnel FETs (TFET) in designing ultra-low power embedded memory bit cells, namely, Static Random Access Memory (SRAM) and embedded Dynamic RAM (eDRAM). A Technology CAD (TCAD)-based model of 22-nm Si/Ge TFET is designed and coupled with mixed-mode circuit simulation. The circuit-level analysis is performed to study the standby power, performance, and robustness characteristics of TFET SRAM and eDRAM. The results are compared with 22 nm FinFET-based design. The analysis shows that at higher performance targets, TFET-based embedded memory consumes higher standby energy; however, the energy-efficiency of TFET is much better when compared at reduced performance targets. Moreover, it is observed that the cell and array level circuit design strategies that exploit unique TFET properties can help improve robustness at low power regimes.

Energy-efficient neural image processing for Internet-of-Things edge devices

Enhancing energy/resource efficiency of neural networks is critical to support on-chip neural image processing at Internet-of-Things edge devices. This paper presents recent technology advancements towards energy-efficient neural image processing. 3D integration of image sensor and neural network improves power-efficiency with programmability and scalability. Computation energy of feedforward and recurrent neural networks is reduced by dynamic control of approximation, and storage demand is reduced by image-based adaptive weight compression. Emerging devices such as tunnel FET and Resistive Random Access Memory are utilized to achieve higher computation efficiency than CMOS-based designs.

Reconfigurable 96×128 active pixel sensor with 2.1µW/mm 2 power generation and regulated multi-domain power delivery for self-powered imaging

We present an energy harvesting system comprising a dual purpose CMOS active pixel sensor (APS) array, and a combined energy extractor and multi domain voltage regulator on a single die in 130nm technology. The reconfigurable image sensor is a 128 × 96 pixel array. The array captures image and is reconfigured to form an on-chip photovoltaic cell to harvest energy. It generates 2.1μW peak power at 300mV with 200klux illuminance. The generated voltage is used as the input of the switching energy extractor that boosts the voltage up to 3.3V and stores the energy in the storage element (battery/super capacitor). The stored energy is then supplied to the load at three independent domains using the single inductor multi-output (SIMO) buck regulator. Both the SIMO buck and the energy-harvesting boost use the only inductor in the system through internally managed time-multiplexing mechanism. This prototype demonstrates a solution for low frame rate, energy autonomous imaging applications including distributed wireless sensor node and IoT electronics.

A tunnel-FET SRAM array for energy-efficient embedded memory blocks in reconfigurable computing platforms

This paper studies the potential of Si-Ge TFET for low-power embedded memory blocks in reconfigurable platforms. The key observations from the comparative analysis of FinFET and TFET based EMB are summarized in Fig. 14. At low frequency, switching to the TFET cell from FinFET provides lower read power but degrades read stability, which can be improved through circuit techniques (TFETB). However, as the frequency increases, the TFET advantages begin to decrease, and eventually for high frequency target TFET may become more power hungry than FinFET. The analysis shows the potential of using TFET for designing memory for low-power reconfigurable platform with relaxed performance targets.