Amit Ranjan Trivedi

Exploring tunnel-FET for ultra low power analog applications: a case study on operational transconductance amplifier

This work studies the potentials and challenges of designing ultra low-power analog circuits exploiting unique characteristics of Tunnel-FET (TFET). TFET can achieve ultra-low quiescent current (~pA). In the subthreshold operation, TFET exhibit subthreshold swing lower than 60mV/decade, and hence higher transconductance per bias current than the MOSFET. TFET also exhibit very weak temperature dependence, and higher output resistance. Among several challenges, TFET demonstrate higher Shot noise at low biasing current. Through design of TFET based Operational Transconductance Amplifier (OTA) these challenges and opportunities are discussed. For implantable bio-medical applications, TFET OTA based neural amplifier design is studied.

Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative Memory

This paper studies the application of tunnel FET (TFET) in designing a low power and robust cellular neural network (CNN)-based associative memory (AM). The lower leakage, steeper switching slope, and higher output resistance of TFET are exploited in designing an ultralow-power TFET-based operational transconductance amplifier (OTA). A TFET-OTA is utilized as a programmable synaptic weight multiplier for CNN. The ultralow-power of TFET-OTA enables a higher connectivity network even at a lower power, and thereby improves the memory capacity and input pattern noise tolerance of CNN-AM for low power applications. The TFET-based higher connectivity CNN also exploits the unique characteristics of TFET to improve the throughput efficiency of CNN-AM.

RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications

A single-pole double-throw novel switch device in0.18¹m SOI complementary metal-oxide semiconductor(CMOS) process is developed for 0.9 Ghz wireless GSMsystems. The layout of the device is optimized keeping inmind the parameters of interest for the RF switch. A subcircuitmodel, with the standard surface potential (PSP) modelas the intrinsic FET model along with the parasitic elementsis built to predict the Ron and Coff of the switch. Themeasured data agrees well with the model. The eight FETstacked switch achieved an Ron of 2.5 ohms and an Coff of180 fF.

Potential of Ultralow-Power Cellular Neural Image Processing With Si/Ge Tunnel FET

This letter studies the application of tunnel FET (TFET) for ultralow power image processing through cellular neural network (CNN). Through steeper switching slope, and thereby higher gm/IDS, a TFET-based CNN synapse can deliver the same performance as MOSFET even with a lower power. A TFET-based synapse is also scalable to the ultralow power regime; hence, by comprising more cells than MOSFET at the same power, TFET can reduce the multiplexing overheads in image processing with CNN. Utilizing unique properties of TFET, we show an improved performance for low power image processing using TFET.

Ultra-low power electronics with Si/Ge tunnel FET

Si/Ge Tunnel FET (TFET) with its subthermal subthreshold swing is attractive for low power analog and digital designs. Greater Ion/Ioff ratio of TFET can reduce the dynamic power in digital designs, while higher gm/IDS can lower the bias power of analog amplifier. However, the above benefits of TFET are eclipsed by MOSFET at a higher power/performance point. Ultra low power scalability of the key analog and digital circuits, SRAM and operational transconductance amplifier (OTA), with TFET is demonstrated. Analyzing a TFET based cellular neural network, this work shows the feasibility of ultra-low-power neuromorphic computing with TFET.

A Simulation Study of Oxygen Vacancy-Induced Variability in

Deposition of a metal gate on high-K dielectric HfO2 is known to generate oxygen vacancy (OVs) defects. Positively charged OVs in the dielectric affect the gate electrostatics and modulate the effective gate workfunction (WF). Count and spatial allocation of OVs varies from device-to-device and induces significant local variability in WF and Vth. This paper presents the statistical models to simulate OV concentration and placement depending on the gate formation conditions. OV-induced variability is studied for SOI FinFET, and compared against the other sources of variability across the technologies. The implications of gate first and gate last processes to the OV concentration/distribution are studied. Simulations show that with channel length and gate dielectric thickness scaling, the OV-induced variability becomes a significant concern.

{\rm HfO}_{2}

We analyze the bias and frequency dependent capacitance of the Power/Ground (P/G) Through-Silicon-Via (TSVs) and its impact on the high-frequency noise in the power delivery network (PDN) of a 3D stack. We show that the P/G TSVs in a 3D PDN act as on-chip distributed decoupling capacitances and hence, help reduce the high-frequency impedance. We present that for the same cross-sectional area, P/G TSVs created using a cluster of small diameter TSVs has higher capacitance than a single large diameter TSV and hence, can further reduce the high-frequency PDN impedance.

/Metal Gated SOI FinFET

This letter studies the interaction of the potential of through-oxide-via (TOV) and the electrical behavior of neighboring transistors in a 3-D stack of fully depleted silicon-on-insulator (FDSOI) devices. Using device simulation, we show that the back-gate electric field of FDSOI devices can be significantly modulated by the potential of TOVs placed in close proximity. Consequently, the change in the TOV potential results in appreciable variation in the threshold voltage and the leakage current of neighboring FDSOI devices.

Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

We compare the performance of static random access memory (SRAM) cells based on negative capacitance (NC) FinFETs and reference FinFETs at the 7-nm technology node. We use a physics-based model for NC FinFETswhere we couple the Landau–Khalatnikovmodel of ferroelectric materials with the standard BSIM-CMG model of FinFET. For the reference FinFETs, we use the predictive model parameters optimized for SRAM design as per the ASAP7 PDK. We exploit the unique characteristics of NC-FinFETs and demonstrate that for ferroelectric thickness below a critical value, SRAMs with higher hold and read stability, better write-ability, lower leakage as well as faster read access time can be designed at the cost of increased write delay.

Through-Oxide-Via-Induced Back-Gate Effect in 3-D Integrated FDSOI Devices

The Toffoli–Fredkin (TF) gate is a universal reversible logic gate capable of performing logic operations without dissipating energy. Here, we show that a linear array of three quantum dots, each hosting a single electron, can realize the TF gate, if we encode logic bits in the spin polarization of the electrons and allow nearest neighbor exchange coupling. The dynamics of the TF gate is realized by selectively driving spin resonances in the coupled spin system with an ac magnetic field. The conditions for gate operation are established, and an estimate of the switching speed and gate error are provided.