Jofre Pallarès

All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis

We report on the detailed electrical investigation of all-inkjet-printed thin-film transistor (TFT) arrays focusing on TFT failures and their origins. The TFT arrays were manufactured on flexible polymer substrates in ambient condition without the need for cleanroom environment or inert atmosphere and at a maximum temperature of 150 °C. Alternative manufacturing processes for electronic devices such as inkjet printing suffer from lower accuracy compared to traditional microelectronic manufacturing methods. Furthermore, usually printing methods do not allow the manufacturing of electronic devices with high yield (high number of functional devices). In general, the manufacturing yield is much lower compared to the established conventional manufacturing methods based on lithography. Thus, the focus of this contribution is set on a comprehensive analysis of defective TFTs printed by inkjet technology. Based on root cause analysis, we present the defects by developing failure categories and discuss the reasons for the defects. This procedure identifies failure origins and allows the optimization of the manufacturing resulting finally to a yield improvement.

Development of a standard cell library and ASPEC design flow for Organic Thin Film Transistor technology

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): 1)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.

A fully-automated methodology and system for printed electronics foil characterization

This paper presents a new characterization setup for Printed Electronics. The proposed system allows automatic generation of experiments, optical and electrical characterization, and statistical result analysis of full printed foils. Although its primary objective is the extraction of the needed post-layout corrections, due to its modular design, it can extract other technology information, like Design Rule values or overall printing quality of the whole fabrication process.

A Systematic Study of Pattern Compensation Methods for All-Inkjet Printing Processes

Inkjet printed electronics is a promising technology for low-cost, flexible, and large area manufacturing of electronic systems. This paper presents a complete characterization methodology, automated and capable of extracting key technology parameters from a large amount of samples. We used this methodology to extract viable compensation strategies for a particular printer, ink, and substrate, analyzing more than a half million structures with a very low human interaction. The results show a promising improvement in yield and fidelity of printed patterns, when using an optimal compensation pattern. As an example, the fabrication yield for 120-μm width-40-μm separation structures raised from less than 10% up to 100% after applying compensations.

A 1.2V 130μA 10-bit MOS-Only Log-Domain ΣΔ Modulator

This paper presents a new low-voltage MOS-only circuit technique to implement oversampling ΣΔ modulators in purely digital CMOS technologies. The basis of the proposed design strategy is a combination of log domain processing and the MOSFET operating in subthreshold. In this sense, compact circuit implementations are given for all the required basic building blocks, such as compressors, integrators, quantizers and DACs. Finally, experimental results are presented for a complete 4th-order 64-oversampling 1-bit ΣΔ modulator integrated using a standard 0.35μm 1-polySi 3-metal digital CMOS technology.

Inkjet-Configurable Gate Arrays (IGA)

Implementation of organic digital circuits (or printed electronic circuits) has been under an extensive investigation, facing some critical challenges such as process variability, device performance, cell design styles and circuit yield. Failure in any single Organic Thin Film Transistor (OTFT) often causes the whole circuit to fail since integration density is still low. For the same reason, the application of fault tolerant techniques is not that popular in these circuits. In this paper, we propose an approach for the direct mapping of digital functions on top of new prefabricated structures: Inkjet-Configurable Gate Arrays (IGA). This alternative has two main advantages. First, it helps to obtain high yield circuits out of mid-yield foils, and second, it allows implementing individual circuit personalization at a very low cost by using additive mask-less printing techniques thus avoiding the need for OTPROM-like (or E2PROM) devices. All along the design process of IGA cells and structures we used the scalability and technology-independent strategies provided by parameterizable cells (PCell) what helps dealing with current fast technology evolution.

Development of Digital Application Specific Printed Electronics Circuits: From Specification to Final Prototypes

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.

Top-down design flow for application specific printed electronics circuits (ASPECs)

This paper presents a top-down approach for the design process of digital Application Specific Printed Electronics (PE) Circuits (ASPECs); from functionality specification at circuit level (i.e. HDL), through the optimization of combinational circuitry (represented by their logical equations), according to the PMOS-based technology that will be used to build a set of Standard Cells (SC) or use a predesign Inkjet Gate Array (IGA), down to the Place and Route to get the final circuit layout. This process will use the technology coming from the Centre for Process Innovation (CPI). This methodology maps the existing ASIC one by updating design styles and cost functions. Thus, it is portable to different Printed Electronics processes, using state-of-the-art logic synthesis EDA/software tools being the main optimization goal the transistor count. Main reason is that printed electronics technologies show low density and not such high yield compared to traditional Silicon-based microelectronics. To illustrate this methodology, we use the design and implementation of the TicTacToe game to be implemented together with flexible textile pressure sensor and lighting.

Modeling all-MOS log filters and its application to /spl Sigma//spl Delta/ modulators

This paper presents new high-level modeling techniques to improve the simulation speed of general all-MOS Log-domain filters, and particularly /spl Sigma//spl Delta/ modulators. A complete set of high-level basic building blocks are obtained from accurate analytical analysis at transistor level using advanced MOS device models. As a result, design verification for this type of circuits can be accelerated by more than 500 times respect to classical transistor-level simulation through SPICE-like engines, while preserving realistic accuracy. Examples are given for a digital 0.35/spl mu/m CMOS technology.

An academic EDA suite for the full-custom design of mixed-mode integrated circuits

This paper proposes a free and complete EDA framework for teaching CMOS full-custom design of mixed-signal integrated circuits. The presented set of EDA tools and associated physical design kit should allow students to gain hands-on experience on schematic entry, both at system and circuit levels, HDL system simulation and block specification, automatic circuit optimization, PCell-based netlist-driven layout, interactive DRC, LVS, 3D parasitics extraction, post-layout simulation and tape-out. A case study based on a ΔΣ modulator for ADC in a simple CMOS technology is supplied to illustrate the capabilities of the proposed environment. Students can easily make use of the presented EDA framework both at laboratory and at home, since all tools are available for both MS Windows and Linux platforms.