Mohammad R. Mirabedini

STI stress-induced increase in reverse bias junction capacitance

A new contribution to reverse-biased junction capacitance is reported. This component arises from trench isolation stress-induced bandgap narrowing that changes the built-in potential. Experimental junction capacitance measurements show good correlation to simulated oxidation stresses. The reported data agrees well with the predicted values from basic device equations. Stress induced capacitance increase of 12% (7.5%) at 3.3 V reverse bias for p/sup +//n (n/sup +// p) junctions, respectively is observed. In addition, well-understood reverse junction leakage relation to stress is also reported. This phenomenon will become increasingly important as trenches become shallower and more tightly spaced.

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.

65 nm Transistors for a 90 nm CMOS SOC Platform

Transistors with 65nm physical gate length for a 90 nm node CMOS technology are reported. Current drive of 775/270 A/ m (Ioff=30nA/ m) at 1V was achieved for N/P-Ch transistors using a 16 Å oxynitrided gate dielectric to reduce the gate leakage current. The Nchannel performance is one of the highest reported thus far. Also, impact of process improvements including pre-gate surface clean, choice of contact ILD material and salicide on the transistor performance was demonstrated. These improvements were used to achieve a higher current drive at a fixed off-state leakage current.

A study of nitrogen peak location in gate oxides grown on nitrogen implanted substrates and its impact on boron penetration

This work investigates properties of gate oxides grown on nitrogen-implanted substrates. It was demonstrated that the location of nitrogen peak in the gate oxide, once fixed at the beginning of the oxidation step, does not change with continued oxidation. Using this property, nitrogen peak was engineered near the gate oxide interface with substrate and was shown to suppress boron penetration more effectively without any significant degradation of the channel mobility in comparison to the case where the nitrogen peak is located within the bulk of the gate oxide.

Impact of Shallow Trench Liner Oxidation Scheme on Junction Leakage

Shallow trench liner oxidation scheme is shown to have direct bearing on the reverse biased junction leakage. Experiments reducing liner oxide thickness and nitride undercut while increasing effective active area actually reduced the leakage currents by 40%. Silicided and unsilicided area, corner and perimeter intensive diodes all exhibited this behaviour. The perimeter component of leakage was most affected by liner oxidation scheme. Simulations of the oxidation process indicate a correlation between stress induced during the liner options and junction leakage.

Radiation Characteristics of a 0.11μm Modified Commercial CMOS Process

The authors present radiation data, total ionizing dose and single event effects, on the LSI logic 0.11 μm commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee single event latch up immunity.

Impact of the interaction between nitrogen implant and NO anneal on narrow-width transistors

This study reports a new behavior in narrow-width transistors resulting from the interaction of oxides grown with nitrogen implant with the nitridation associated with growing other oxides. Nitric oxide (NO) annealing of 28-/spl Aring/ oxides grown on nitrogen-implanted silicon results in the decrease of NMOS threshold voltage and in the increase (absolute value) of PMOS threshold with decreasing width. This effect arises from the positive charge from NO anneal interacting with the parasitic transistor associated with the shallow trench isolation edge recess. The parasitic impact becomes more pronounced for narrower widths due to higher effect of recess on total transistor width.

Radiation evaluation of a 0.18 μm commercial CMOS process and modified radiation hardened versions of this process

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logics commercial 0.18 μm process and its radiation hardened version. Test results, are discussed in this paper. No Single Event Latch-up (SEL) was observed up to a LET of 75 MeVcm2/mg for radiation hardened version, while the commercial process was very sensitive to SEL.

X-ray and secondary ion mass spectrometry investigation of activation behavior of self-preamorphized silicon substrate

The junctions for p-type source/drain and extensions for sub-100 nm technology nodes can be formed by using low energy beamline implantation, plasma doping, or elevated source/drain approaches in conjunction with various thermal processing methods. An important objective for sub-100 nm junction engineering is incorporation and activation of desired level of dopant in the junction region. In this article, the interaction between Si preamorphization implantation and boron implantation has been investigated by using secondary ion mass spectrometry (SIMS), triple crystal x-ray diffraction (XRD), and four point probe measurements. The dopant profile abruptness is found to be a function of boron energy and the Si+ ion dose and energy. Results demonstrate that an increase in Si energy by 10 keV yields ∼100 A shallower and more abrupt boron profiles. Crystallinity of the implanted layer after thermal treatment has been characterized by the triple crystal XRD technique. The XRD rocking curve data correlated well w...

A 90 nm CMOS technology with modular quadruple gate oxides for advanced SoC applications

This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.