Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Verne Hornback is active.

Publication


Featured researches published by Verne Hornback.


Journal of The Electrochemical Society | 2005

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Wai Lo; Hong Lin; Wei-jen Hsia; Colin Yates; Verne Hornback; Jim Elmer; Wilbur G. Catabay; Mohammad R. Mirabedini; Venkatesh P. Gopinath; Erhong Li; David Pachura; Joyce Lin; Lesly Duong; Sharad Prasad; Masanobu Matsunaga; Toshitake Tsuda

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.


Journal of The Electrochemical Society | 2005

Process Characterization and Control of Polycrystalline SiGe as the Gate Electrode in CMOS Fabrication

Hong Lin; Wai Lo; Shiqun Gu; Verne Hornback; Jim Elmer; Wilbur G. Catabay

Polycrystalline Si 1 - x Ge x (poly-SiGe) films have been proposed as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal-oxide-semiconductor (CMOS) field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion than that of poly-Si gate. The use of Poly-SiGe as the gate electrode, however, has serious implications on transistor fabrication processes such as plasma dry etching, resist ashing, wafer cleaning, and oxidation. In this work, we investigate the impact of these processes on the polycrystalline Si 1 - x Ge x profile and the critical dimension (CD) of the gate electrode. The process improvements and an integration scheme using an oxide liner are presented to minimize the profile and CD variations introduced by the fabrication processes.


radiation effects data workshop | 2006

Radiation Characteristics of a 0.11μm Modified Commercial CMOS Process

Christian Poivey; Hak S. Kim; Melanie D. Berg; Jim Forney; Christina M. Seidleck; Miguel A. Vilchis; Anthony M. Phan; Tim Irwin; Kenneth A. LaBel; Rajan K. Saigusa; Mohammad R. Mirabedini; Rick Finlinson; Agajan Suvkhanov; Verne Hornback; Jun Song; Jeffrey Tung

The authors present radiation data, total ionizing dose and single event effects, on the LSI logic 0.11 μm commercial process and two modified versions of this process. Modified versions include a buried layer to guarantee single event latch up immunity.


IEEE Electron Device Letters | 2003

Impact of the interaction between nitrogen implant and NO anneal on narrow-width transistors

Venkatesh P. Gopinath; Arvind Kamath; Mohammad R. Mirabedini; Verne Hornback; Ynhi Le; Alfred Badowski; Wen-Chin Yeh

This study reports a new behavior in narrow-width transistors resulting from the interaction of oxides grown with nitrogen implant with the nitridation associated with growing other oxides. Nitric oxide (NO) annealing of 28-/spl Aring/ oxides grown on nitrogen-implanted silicon results in the decrease of NMOS threshold voltage and in the increase (absolute value) of PMOS threshold with decreasing width. This effect arises from the positive charge from NO anneal interacting with the parasitic transistor associated with the shallow trench isolation edge recess. The parasitic impact becomes more pronounced for narrower widths due to higher effect of recess on total transistor width.


european conference on radiation and its effects on components and systems | 2005

Radiation evaluation of a 0.18 μm commercial CMOS process and modified radiation hardened versions of this process

Christian Poivey; Hak S. Kim; Jim Forney; Kenneth A. LaBel; Rajan K. Saigusa; Miguel A. Vilchis; Rick Finlinson; Agajan Suvkhanov; Verne Hornback; Jun Song; Jeffrey Tung; Mohammad R. Mirabedini

We present radiation data, Total Ionizing Dose and Single Event Effects, on the LSI Logics commercial 0.18 μm process and its radiation hardened version. Test results, are discussed in this paper. No Single Event Latch-up (SEL) was observed up to a LET of 75 MeVcm2/mg for radiation hardened version, while the commercial process was very sensitive to SEL.


Journal of Vacuum Science & Technology B | 2004

X-ray and secondary ion mass spectrometry investigation of activation behavior of self-preamorphized silicon substrate

Agajan Suvkhanov; Mohammad R. Mirabedini; Verne Hornback; Zhihao Chen

The junctions for p-type source/drain and extensions for sub-100 nm technology nodes can be formed by using low energy beamline implantation, plasma doping, or elevated source/drain approaches in conjunction with various thermal processing methods. An important objective for sub-100 nm junction engineering is incorporation and activation of desired level of dopant in the junction region. In this article, the interaction between Si preamorphization implantation and boron implantation has been investigated by using secondary ion mass spectrometry (SIMS), triple crystal x-ray diffraction (XRD), and four point probe measurements. The dopant profile abruptness is found to be a function of boron energy and the Si+ ion dose and energy. Results demonstrate that an increase in Si energy by 10 keV yields ∼100 A shallower and more abrupt boron profiles. Crystallinity of the implanted layer after thermal treatment has been characterized by the triple crystal XRD technique. The XRD rocking curve data correlated well w...


Archive | 1999

Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET

John J. Seliskar; Verne Hornback; David W. Daniel


Archive | 2003

Fabrication of trenches with multiple depths on the same substrate

Mohammad R. Mirbedini; Venkatesh P. Gopinath; Hong Lin; Verne Hornback; Dodd Defibaugh; Ynhi Le


Archive | 2005

Self-aligned cell integration scheme

Richard Carter; Hemanshu D. Bhatt; Shiqun Gu; Peter A. Burke; James R. B. Elmer; Sey-Shing Sun; Byung-Sung Kwak; Verne Hornback


Archive | 2000

Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same

Derryl D. J. Allman; John Q. Walker; Verne Hornback; Todd A. Randazzo

Collaboration


Dive into the Verne Hornback's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Hak S. Kim

Goddard Space Flight Center

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Jim Forney

Goddard Space Flight Center

View shared research outputs
Top Co-Authors

Avatar

Kenneth A. LaBel

Goddard Space Flight Center

View shared research outputs
Researchain Logo
Decentralizing Knowledge