Venkatesh P. Gopinath

STI stress-induced increase in reverse bias junction capacitance

A new contribution to reverse-biased junction capacitance is reported. This component arises from trench isolation stress-induced bandgap narrowing that changes the built-in potential. Experimental junction capacitance measurements show good correlation to simulated oxidation stresses. The reported data agrees well with the predicted values from basic device equations. Stress induced capacitance increase of 12% (7.5%) at 3.3 V reverse bias for p/sup +//n (n/sup +// p) junctions, respectively is observed. In addition, well-understood reverse junction leakage relation to stress is also reported. This phenomenon will become increasingly important as trenches become shallower and more tightly spaced.

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.

65 nm Transistors for a 90 nm CMOS SOC Platform

Transistors with 65nm physical gate length for a 90 nm node CMOS technology are reported. Current drive of 775/270 A/ m (Ioff=30nA/ m) at 1V was achieved for N/P-Ch transistors using a 16 Å oxynitrided gate dielectric to reduce the gate leakage current. The Nchannel performance is one of the highest reported thus far. Also, impact of process improvements including pre-gate surface clean, choice of contact ILD material and salicide on the transistor performance was demonstrated. These improvements were used to achieve a higher current drive at a fixed off-state leakage current.

Impact of Shallow Trench Liner Oxidation Scheme on Junction Leakage

Shallow trench liner oxidation scheme is shown to have direct bearing on the reverse biased junction leakage. Experiments reducing liner oxide thickness and nitride undercut while increasing effective active area actually reduced the leakage currents by 40%. Silicided and unsilicided area, corner and perimeter intensive diodes all exhibited this behaviour. The perimeter component of leakage was most affected by liner oxidation scheme. Simulations of the oxidation process indicate a correlation between stress induced during the liner options and junction leakage.

Impact of the interaction between nitrogen implant and NO anneal on narrow-width transistors

This study reports a new behavior in narrow-width transistors resulting from the interaction of oxides grown with nitrogen implant with the nitridation associated with growing other oxides. Nitric oxide (NO) annealing of 28-/spl Aring/ oxides grown on nitrogen-implanted silicon results in the decrease of NMOS threshold voltage and in the increase (absolute value) of PMOS threshold with decreasing width. This effect arises from the positive charge from NO anneal interacting with the parasitic transistor associated with the shallow trench isolation edge recess. The parasitic impact becomes more pronounced for narrower widths due to higher effect of recess on total transistor width.

Effects of Stress-Induced Bandgap Narrowing on Reverse-Bias Junction Behavior

The effects of bandgap narrowing due to stress generated during Shallow Trench Isolation (STI) are analyzed. Reverse-bias junction leakage and capacitance measurements are correlated to results from device simulation. A locally varying stress dependent bandgap model is implemented to understand the influence of stress effects. Increases in both junction capacitance and leakage agree well with experiments. Results of leakage and capacitance on the 0.18 m and 0.09 m technologies indicate that effects of process induced stress on device behavior need careful attention.

A 90 nm CMOS technology with modular quadruple gate oxides for advanced SoC applications

This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.

Method of increasing gate nitridation and its impact on CMOS devices

A process that combines shallow nitrogen implant with rapid thermal nitridation is shown to double the nitrogen content in ultra-thin oxynitrides for the same EOT. Implanted nitrogen acts as a second source of nitrogen during gate dielectric formation and amount of incorporated nitrogen is directly proportional to the implant dose. Nitridation is shown to have opposite effects on N and PMOS mobilities. PMOS mobilities show a continuous decrease with increasing gate nitrogen content. In addition, increasing nitridation leads to severe NBTI effect on PMOS devices. Therefore, a trade-off between boron penetration resistance and performance for PMOS transistors is indicated.