Mohammed Abdulaziz

A Compensation Technique for Two-Stage Differential OTAs

In this brief, a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3-dB bandwidth, the unity gain frequency, and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole. The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values, which makes it attractive for low-power applications with low area overhead.

A 3.4mW 65nm CMOS 5 th order programmable active-RC channel select filter for LTE receivers

In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm CMOS technology with a core area of 0.29mm2. Its total current consumption is 2.83mA from a 1.2V supply. The measured input referred noise is 39nV/√Hz, the in-band IIP3 is 21.5dBm, at the band-edge the IIP3 is 20.7dBm, the out-of-band IIP3 is 20.6dBm, and the compression point is 0dBm.

A positive feedback passive mixer-first receiver front-end

This paper presents a technique to reduce the noise figure of a passive mixer-first receiver front-end. By using lower than 50Ω switch resistance in the current-mode passive mixer and introducing a positive feedback from baseband to the RF-input, it can be well matched close to fLO while achieving a noise figure below 3dB, which is otherwise a fundamental limit. A quadrature front-end prototype for a direct conversion receiver has been implemented in 65nm CMOS, occupying an active area of 0.23mm2 with a frequency operation ranging from 0.7 to 3.8 GHz. The prototype achieves a minimum noise figure of 2.5dB, an out-of-band 1dB compression point of +3dBm, with IIP3 and IIP2 exceeding +26 and +65dBm, respectively. The current consumption from a 1.2V supply is between 22.8 and 62.8mA, depending on frequency operation.

CMOS adaptive TIA with embedded single-ended to differential conversion for analog optical links

A variable gain transimpedance amplifier (TIA) is presented featuring single-ended to differential conversion by means of negative feedback. The proposed topology also ensures stability when amplifier gain is varied. Furthermore, effective input capacitance of the TIA is reduced by using a positive capacitive feedback. The circuit is intended for intermediate frequency (IF) over fiber systems, but can be readily adapted for other applications. When simulated with a photodiode capacitance of 1.4 pF, the TIA exhibits a tunable gain range of 51 to 73dBΩ with a bandwidth of 550 MHz. The circuit designed in a standard 65nm CMOS process consuming 4mA from a 1.2V supply, achieves a spurious free dynamic range (SFDR) of 109dB·Hz2/3 at 100 MHz.

A 4 th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOS

Gm-C filters suffer from limited dynamic range due to a trade-off between noise and linearity in OTA design. This paper therefore presents a filter with a linearization technique to break this trade-off. This technique is demonstrated by a low power 4th order 10MHz Butterworth Gm-C low pass filter. The filter was implemented in 65nm CMOS technology with a core area of 0.19mm2 and a total current consumption of 3.5mA from a 1.2V supply. The measured input referred noise is 31nV/√Hz, the maximum in-band IIP3 is 39dBm, the out-of-band IIP3 is 34dBm, and the compression point is 8.2dBm.

A cellular receiver front-end with blocker sensing

A receiver front-end supporting contiguous and non-contiguous intra-band carrier aggregation scenarios with a fully integrated spectrum sensor that can detect both in-gap and out-of-band blockers has been implemented in 65nm CMOS technology. An NF of 2.5dB is achieved using a noise canceling LNTA, and linearized OTAs are used to achieve an IIP3 improvement of up to 6.5dB in-band and 11dB at the filter band edge. The spectrum sensor can detect blocker levels in 22 steps of 9MHz between -100MHz and 100MHz IF. The system consumes between 36.6mA and 57.6mA from a 1.2V supply.

A Digitally Assisted Nonlinearity Mitigation System for Tunable Channel Select Filters

This brief presents a low-complexity system for digitally assisting a channel select filter (CSF) to mitigate both even- and odd-order nonlinearities. The proposed solution is scalable and can be utilized for nonlinearity mitigation in different analog transceiver blocks. The system consists of an auxiliary path with a low-resolution analog to digital converter (ADC) enabling digital recreation and measurement of the distortion in the main path and relies on an adaptive digital signal processing algorithm to detect and tune the analog components to their optimal settings. The system provides robustness against process, voltage, and temperature variations, and the digital part requires an equivalent logic of only 42 k gates in CMOS technology, enabling cost-efficient implementation on integrated circuits. The operation of the system has been verified by using a tunable CSF capable of receiving a 10-MHz baseband signal interfaced to an external ADC. The results demonstrate that the proposed system is capable of tuning the CSF to its optimal bias voltage, providing a third-order intermodulation reduction of 14.5 dB.

Digitally assisted adaptive non-linearity suppression scheme for RF front ends

This paper presents a robust and low-complexity non-linearity suppression scheme for radio frequency (RF) transceiver building blocks to efficiently mitigate intermodulation distortion. The scheme consists of tunable RF components assisted by an auxiliary path equipped with an adaptive digital signal processing algorithm to provide the tuning control. This proposed concept of digitally-assisted tuning is capable of handling a large range of non-linear behaviours without any complexity increase in the expensive RF circuitry and is robust to process, voltage and temperature variations. A case study on the third order intermodulation of the channel select filter for a full 10MHz Long Term Evolution (LTE) reception bandwidth is used to demonstrate the feasibility and effectiveness of the technique.

CMOS Integrated Remote Antenna Unit for Fiber-Fed Distributed MIMO Systems

A fully integrated remote antenna unit (RAU) intended for fiber-fed distributed multiple-input multiple-output systems is presented. The circuit is designed for narrowband (60 MHz) time-division duplex systems, where an IF over fiber approach is chosen to facilitate the use of low-cost optical components and integrated photodetectors. A novel antenna switch control scheme is introduced, which enables the use of an integrated antenna switch instead of a bulky off chip circulator. The reference frequency signal is distributed in the fiber together with user data and used by a phase-locked-loop-based frequency synthesizer to generate the local oscillator signal inside the RAU, hence synchronizing all RAUs of the distributed antenna system. At an operating frequency of 2.1 GHz, the measured optical-to-electrical conversion gain of the downlink is 71.7 dB, the error vector magnitude is 3.2%, and the adjacent channel leakage ratio is 39.2 dBc at an output power of +3 dBm for a 16-quadrature amplitude modulation (16-QAM) long-term evolution downlink signal. The uplink has a gain of 32.5 dB, a noise figure of 3.5 dB, and an in-band third-order intercept point of −12 dBm. Implemented in a standard 65-nm CMOS process, the complete RAU occupies just 2 mm2 of die area and consumes 146 mW during downlink signal transmission and 122 mW during uplink signal reception.

Analog integrated audio frequency synthesizer

In this paper we present an audio synthesizer that creates audio signals, intended to be reproduced as sound by a loudspeaker. This paper details the design, implementation and verification of an analog, subtractive audio synthesizer. The synthesizer produces a variety of waveforms spanning approximately 3 octaves. The frequency is controlled by an external voltage and the harmonic content is regulated by a tunable filter. The system is fabricated in 130 nm CMOS. Current consumption measures between 1.8 and 2.1 mA from a supply of 1.2 V.