Markus Törmänen

A Compensation Technique for Two-Stage Differential OTAs

In this brief, a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3-dB bandwidth, the unity gain frequency, and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole. The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values, which makes it attractive for low-power applications with low area overhead.

A 24-GHz LC-QVCO in 130-nm CMOS using 4-bit switched tuning

A 24 GHz 130-nm CMOS quadrature voltage controlled oscillator using 4-bit switched frequency tuning is presented. It consists of two differential oscillators coupled to oscillate in quadrature through transistors and mutual inductance between the source nodes. The frequency tuning is accomplished by 4 bits controlling an array of MOS varactors in each resonance tank, combined with a small continuously tuned varactor. The oscillator measures a frequency tuning range of 4.3%, and a worst case phase noise over the tuning range of -111.6 dBc/Hz at 1 MHz offset, with a 1.35 V supply and a power consumption of 24 mW.

A 65-nm CMOS ultra-low-power LC quadrature VCO

An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65 nm CMOS process. To minimize power dissipation an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (fo) of 3.8 GHz, was designed. According to SpectreRF simulations the power dissipation is below 250 ¿W at a 0.6V supply. At this supply the simulated tuning range and phase noise at 1 MHz offset are 10.4% (2.34-2.59 GHz) and -113.4 dBc/Hz respectively. The phase noise figure of merit (FoM) is better than 187 dB at all supply voltages of interest, which is competitive to other state-of-the-art QVCOs.

Two 24 GHz receiver front-ends in 130-nm CMOS using SOP technology

Two 24 GHz 130-nm CMOS receiver front-ends using System-on-Package (SOP) technology are demonstrated. CMOS dies featuring a two-stage LNA, a passive mixer, and output buffers are flip-chipped to a glass carrier featuring low loss baluns. One design uses glass baluns for both RF and LO input, whereas the other uses an active RF balun on-chip. The fully differential front-end measures; 20.7dB conversion gain, 7.8dB NF, −23.3dBm CP1dB, −12.6dBm IIP3, 16.3dBm IIP2, and 44dB LO to RF isolation. The single-ended input front-end measures; 14.7dB conversion gain, 8.5dB NF, −21.1dBm CP1dB, −10.4dBm IIP3, 17.6dBm IIP2, and 51dB LO to RF isolation.

A Miniaturized Marchand Balun in CMOS With Improved Balance for Millimeter-Wave Applications

The analysis and design of a millimeter-wave passive balun on silicon substrate with small size and good balance is presented. The reason for the imbalance of the balun is analyzed and a novel method using two grounded T bars beneath the coupled lines to tune the balance is proposed. The balun was fabricated in a 65 nm CMOS process, by using broadside coupled lines with small separation, the length of balun is reduced, resulting in a size of only 0.01 mm2. In the 57-67 GHz band, the measured amplitude imbalance is less than 0.5 dB and the phase imbalance is less than 1 °. This method for optimizing the imbalance of balun is efficient and it does not increase the size of balun.

Tunable duplex filter for adaptive duplexers of advanced LTE handsets

The new generation mobile handsets must support a large number of frequency bands and duplex offsets. Traditionally, an adaptive duplexing technique makes use of a wideband circulator to create initial isolation. A tunable duplex filter is presented in this paper, achieving the required tuning range for LTE Band 1. The demonstrated circuit is implemented in a 250nm Silicon on Sapphire (SOS) process, it provides an isolation of 19dB and 14dB at the transmit and the receive frequencies, respectively. The measured insertion loss from PA to antenna port is better than 3.8dB. The measured third-harmonic suppression is 45.9dB at an input of 24.5dBm. The implemented circuit occupies an area of 3.0mm×2.2mm.

A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching

This paper presents an inductor-less frequency selective input match wireless receiver front-end utilizing noise cancellation, operational from 0.7 to 3.8 GHz. The main path of the receiver consists of a high input impedance transconductance stage where the output is down-converted to baseband by current mode passive mixers, and then amplified to voltage by a transimpedance amplifier. The output voltage is converted into a current and frequency up-converted by a second set of transconductance stage and mixer. This current is then fed back to the input of the main path, reducing the input impedance, providing input match by means of negative feedback. An auxiliary path with digitally controllable gain is also introduced to cancel the noise of the main path while maintaining high linearity. The chip prototype is fabricated in a 65 nm CMOS process and occupies an active area of 0.15 mm 2. It achieves a noise figure between 1.6 dB and 3.2 dB depending on the frequency of operation, and an out-of-band IIP2 and IIP3 better than +75 dBm and +1 dBm, respectively. The chip is supplied by 1.2 V and consumes 22.8-34.9 mA.

A 24-GHz quadrature receiver front-end in 90-nm CMOS

A 24 GHz quadrature receiver front-end in 90-nm CMOS is presented. It consists of a two-stage LNA, passive mixers, and a QVCO. The RF input is single-ended and is converted to differential form in the first LNA stage. The LNA has two bands of operation within the frequency range of the QVCO. The oscillator measures a centre frequency of 23.7 GHz with a 7.2% tuning range, a worst case phase noise over the tuning range of -102 dBc/Hz at 1 MHz offset, and a power consumption of 22 mW. The front-end achieves; 18 dB conversion gain, 8.9 dB NF, -23 dBm ICP1 dB, -11 dBm IIP3, 12 dBm IIP2, and a power consumption of 42 mW (excluding QVCO).

A 1.5 V 28 GHz Beam Steering SiGe PLL for an 81-86 GHz E-Band Transmitter

This letter presents measurement results for a low supply voltage 28 GHz beam steering PLL, designed in a SiGe bipolar process with fT = 200 GHz. The PLL, designed around a QVCO, is intended for a beam steering 81-86 GHz E-band transmitter. Linear phase control is implemented by variable current injection into a Gilbert type phase detector, with a measured nominal phase control sensitivity of 2.5 °/μA. The demonstrated LO generation method offers great advantages in the implementation of beam steering mm-wave transmitters, since only the low frequency PLL reference signal of 1.75 GHz needs to be routed across the chip to the different transmitters. Except for an active loop filter, used to extend the locking range of the PLL, the design uses a low supply voltage of 1.5 V. The PLL obtains a measured in band phase noise of -107 dBc/Hz at 1 MHz offset. The power consumption equals 54 mW from the 1.5 V supply plus 1.8 mW for the variable supply of the active low pass filter.

A positive feedback passive mixer-first receiver front-end

This paper presents a technique to reduce the noise figure of a passive mixer-first receiver front-end. By using lower than 50Ω switch resistance in the current-mode passive mixer and introducing a positive feedback from baseband to the RF-input, it can be well matched close to fLO while achieving a noise figure below 3dB, which is otherwise a fundamental limit. A quadrature front-end prototype for a direct conversion receiver has been implemented in 65nm CMOS, occupying an active area of 0.23mm2 with a frequency operation ranging from 0.7 to 3.8 GHz. The prototype achieves a minimum noise figure of 2.5dB, an out-of-band 1dB compression point of +3dBm, with IIP3 and IIP2 exceeding +26 and +65dBm, respectively. The current consumption from a 1.2V supply is between 22.8 and 62.8mA, depending on frequency operation.