Mohammed Fakhruddin

Hot Carrier Degradation and Performance of 65nm RF n-MOSFET

Hot carrier stress (HCS) induces significant degradation on the performance of 65 nm RF n-MOSFET with minimum poly length (Lpoly). Although the cutoff frequency (Ft) is very high (~212 GHz) for these devices, the high HCS degradation poses a challenge for RF application. Additional effort will be needed to improve the process and/or device to take full advantage of the record n-MOSFET performance.

Interposer FPGA with self-protecting ESD design for inter-die interfaces and its CDM specification

Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.

FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification

Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a 32 Gb/s bit rate. Fast and reliable verification of the custom ESD design was developed based on Calibre PERC schematic checking combined with Calibre DRC design rule checking. Our proposed analytical model shows ∼50% increase of the electric field at the FinFET top compared to planar sidewalls. A higher electric field at the fin-top decreases gate oxide breakdown, reduces RX charged device model (CDM) immunity for the FinFET MPSoC, and brings the RX on par with the TX, CDM-wise.