Vassili Kireev

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET

A 56Gb/s PAM4 wireline transceiver testchip is implemented in 16nm FinFET. The CML transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The receiver consists of continuous-time linear equalizers with constant DC-gain and a 28GSa/s 32-way time-interleaved SAR ADC. The transceiver achieves 1e-8 BER over a backplane channel with 25dB loss at 14GHz while consuming 550mW power, excluding DSP.

A Low-Power 0.5–6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs

This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages and resolve significant challenges with receiver input and transmitter output insertion loss, power integrity, ESD, and reliability. The transceiver clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The receiver front-end utilizes a 3-stage CTLE with wide input common-mode to remove the post-cursor ISI. The CTLE is fully adaptive using an LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The transceiver achieves BER 10-15 at 6.6 Gb/s over a 20 dB loss channel. Power consumption is 129 mW from 1.2 V and 1 V supplies.

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET

A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current mode logic transmitter incorporates an auxiliary current injection at the output nodes to maintain PAM4 amplitude linearity. The ADC-based receiver incorporates hybrid analog and digital equalizations. The analog equalization is performed using two identical stages of continuous time linear equalizer, each having a constant of ~0-dB dc-gain and a maximum peaking of ~7 dB peaking at 14 GHz. A 28-GSample/s 32-way time-interleaved SAR ADC converts the equalized analog signal into digital domain for further equalization using digital signal processing. The transceiver achieves <1e-8 bit error rate over a backplane channel with 31-dB loss at 14-GHz and 3.5-mVrms additional crosstalk, using a fixed ~10-dB TX equalization and an adaptive hybrid RX equalization, with the DSP configured to have a 24-tap feed forward equalizer and a 1-tap decision feedback equalizer. The transceiver consumes 550-mW power at 56 Gb/s, excluding the power of the on-chip configurable DSP that cannot be accurately measured as it is implemented as part of a larger test structure.

Interposer FPGA with self-protecting ESD design for inter-die interfaces and its CDM specification

Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.

FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification

Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a 32 Gb/s bit rate. Fast and reliable verification of the custom ESD design was developed based on Calibre PERC schematic checking combined with Calibre DRC design rule checking. Our proposed analytical model shows ∼50% increase of the electric field at the FinFET top compared to planar sidewalls. A higher electric field at the fin-top decreases gate oxide breakdown, reduces RX charged device model (CDM) immunity for the FinFET MPSoC, and brings the RX on par with the TX, CDM-wise.

A 8–14 GHz varactorless current controlled LC oscillator in 16nm CMOS technology

This paper presents a new concept of fine frequency tuning in a differential LC oscillator by injecting quadrature phase shifted current into the tank that can replace the use of a conventional varactor, eliminating all limitations associated with it, such as specific bias voltage requirement, limited Q-factor, technology/process uncertainties, model accuracy etc. Wide tuning range of 8-14 GHz is achieved by 5-bit switched capacitor array distributed across the exit legs of the inductor. The circuit is implemented in 16nm CMOS technology. Oscillator core consumes 2.85mW power from 0.9V supply at 10GHz frequency for 400mV single-ended swing. Phase noise is - 108dBc/Hz at 1MHz offset for no tuning current injection.

A low-power 6.6-Gb/s wireline transceiver for low-cost FPGAs in 28nm CMOS

This paper describes the design of a 0.5-6.6Gb/s fully-adaptive low-power quad transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs. The receiver front-end utilizes a wide input common-mode circuit and a 3-stage CTLE to remove the immediate post-cursor ISI. The CTLE is fully adaptive using sign-sign LMS algorithm and edge-based equalization. The transmitter utilizes a 3-tap FIR. The clocking network provides continuous operation range up to the maximum speed and incorporates two wide-range ring-based PLLs for enhanced clocking flexibility. The transceiver achieves BER <; 10-15 at 6.6Gb/s over an 18dB loss channel. Power consumption is 129mW from 1.2V and 1V supplies.