James Karp

Graded tunnelling barrier and oxygen concentration in thermally grown ultrathin SiOx gate oxide

Barrier parameters of a thermally grown SiOx gate oxide are derived by relating the SIMS oxygen concentration profile to the barrier height. Even in the simple analytical form such a graded barrier model agrees with the tunnelling current and its voltage dependence in both directions. Asymmetrical tunnelling I?Vs in the symmetrical n+Si?SiOx?n+Si structure are due to both graded barrier and penetration of carriers into the gate oxide at the SiOx?Si substrate interface.

Current through SiO2 gate oxide and its low frequency fluctuations: Trapping on charged dangling bonds with negative Hubbard U

An estimate of Hubbard U supports instability of neutral one-electron Si dangling bonds in SiO2 and the formation of charged two-electron and two-hole negative U centers through the reaction Si•+Si•→Si++Si−••. The trapping on these negative U centers creates and annihilates “dents” in the thin barrier for electron and hole tunneling through the gate oxide. Such dents are visible as gate current low frequency fluctuations (1∕f noise). The longer trapping time of holes causes irreversible Si−••→Si+ conversion, which leads to stress-induced leakage current and accumulation of positive charge in the oxide under voltage stress.

Neutron, 64 MeV Proton, Thermal Neutron and Alpha Single-Event Upset Characterization of Xilinx 20nm UltraScale Kintex FPGA

The single-event response of Xilinx 20nm UltraScale Kintex FPGA is characterized using neutron, 64 MeV proton, thermal neutron and alpha foil irradiation sources. Single-event upset and multi-bits upset results are presented.

Understanding degradation and breakdown of SiO2 gate dielectric with “negative Hubbard U” dangling bonds

Degradation and time dependent breakdown of SiO2 gate oxides are discussed based on the Anderson–Mott theory of amorphous solids with dangling bonds as diamagnetic “negative Hubbard U” centers. Negative-U dangling bonds in the oxide are either positive D+ centers or two-electron negative D− centers. Due to a large difference in mobility between electrons and holes, hopping current in SiO2 is mainly electron current on D+ centers. Degradation of isolation properties and time dependent breakdown of SiO2 gate oxide under voltage stress are due to the conversion of D− into D+ centers caused by the hole-hopping current in SiO2. The reaction of conversion is stress polarity dependent. Thermal conductivity of Si is approximately 100 times higher than thermal conductivity of SiO2. Heat dissipation and accumulation of D+ centers inside the oxide are important in understanding the time dependent breakdown of the oxide.

Hot Carrier Degradation and Performance of 65nm RF n-MOSFET

Hot carrier stress (HCS) induces significant degradation on the performance of 65 nm RF n-MOSFET with minimum poly length (Lpoly). Although the cutoff frequency (Ft) is very high (~212 GHz) for these devices, the high HCS degradation poses a challenge for RF application. Additional effort will be needed to improve the process and/or device to take full advantage of the record n-MOSFET performance.

Dangling bonds with “negative Hubbard U ”: Physical model for degradation of SiO2 gate dielectric under voltage stress

A model proposed to explain the phenomenon of current increase and its fluctuation under voltage stress in a SiO2 gate dielectric is based on the amorphous nature and presence of dangling bonds in SiO2. Dangling bonds D0 are thought to be negative-U centers, where their neutral state is unstable and therefore a spontaneous reaction of charge disproportionation take place: D0+D0→D++D−. As a result, a SiO2 amorphous network has diamagnetic positive D+ and negative D− centers. Due to a large difference in mobility between electrons and holes, hopping current in SiO2 is mainly electron current on D+ centers. Current increase and fluctuation under a voltage stress is due a conversion of D− into D+ centers by the hole component of current through SiO2 gate dielectric. This conversion is an irreversible process accelerated by temperature and electric field.

Impact of Temperature and Vcc Variation on 20nm Kintex UltraScale FPGAs Neutron Soft Error Rate

The single-event response vs. temperature and Vcc supply voltage of the 20nm Kintex UltraScale FPGA is characterized using a 64 MeV proton beam as proxy for atmospheric neutron. Single-event upset and multi-bit upset results are presented.

Latchup in bulk FinFET technology

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

Interposer FPGA with self-protecting ESD design for inter-die interfaces and its CDM specification

Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100-200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2.5D assembly. Bare die self-capacitance is introduced as a CDM modeling parameter in the environment of 3D/2.5D assembly. HBM/CDM qualification with respect to the S20.20-2014 standard is demonstrated for self-protecting die-to-die IOs in the second generation 20nm interposer FPGA.

FinFET MPSoC 32 Gb/s transceivers: Custom ESD protection and verification

Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a 32 Gb/s bit rate. Fast and reliable verification of the custom ESD design was developed based on Calibre PERC schematic checking combined with Calibre DRC design rule checking. Our proposed analytical model shows ∼50% increase of the electric field at the FinFET top compared to planar sidewalls. A higher electric field at the fin-top decreases gate oxide breakdown, reduces RX charged device model (CDM) immunity for the FinFET MPSoC, and brings the RX on par with the TX, CDM-wise.