Mohsin M. Tarar

Enhanced gain bandwidth and loss compensated cascaded single-stage CMOS distributed amplifier

This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in commercial 65nm CMOS technology. The CSSDA is composed of three distributed stages connected in a cascade configuration to target high gain. The idle interstage drain terminations are omitted because of multiplicative gain mechanism. High gain is maintained over very large bandwidth through the inductive-peaking technique. Further, the CSSDA single cell is modified by a loss compensation technique to remove the high frequency losses of the artificial transmission lines which shows a significant enhancement in gain bandwidth (GBW) product. The simulation results show a GBW of 540GHz for the loss compensated CSSDA (LC-CSSDA) which is significantly higher than GBW of 350 GHz for a conventional CSSDA. The 2-stage (LC-CSSDA) shows a GBW of 835GHz which is almost twice the GBW (426 GHz) of a conventional 2-stage CSSDA.

Efficient 2–16 GHz flat-gain stacked distributed power amplifier in 0.13μm CMOS using uniform distributed topology

This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13um CMOS technology. To obtain high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate due to voltage division between gate-source capacitance, Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2 −16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm2.

A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS

This work presents the design and implementation of a fully integrated broadband medium power stacked amplifier in 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack to increase the output voltage swing along with the output impedance. The load impedance is further optimized with a resistive feedback which not only results in broadband operation but also avoids a lossy broadband output matching network which reduces area significantly. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier shows a measured peak saturated output power from 13 dBm to 8.5 dBm and a P1dB of 7 dBm to 4 dBm from 0.3 GHz to 10 GHz. The measured gain is 9 dB with a gain ripple of ±1.5 dB in the entire frequency range, yielding a fractional bandwidth of 188%. The measured load-pull -1 dB, -2 dB output power contours verify the optimum impedance around 50 Ω. The active chip area is only 0.44mm2.

Stacked inverter-based amplifier with bandwidth enhancement by inductive peaking

This paper presents a stacked inverter-based amplifier in a commercial 65nm CMOS technology. The proposed amplifier, based on an inverter, uses stacking to achieve high output swing and distributed inductive peaking to obtain ultra-wide bandwidth. Furthermore, the proposed topology is generalized for more stacked transistors for high output swing requirement which then utilizes distributive peaking inductors to maintain that swing over a large bandwidth. The simulated output swing for a 2-, 4- and 6-stacked amplifier is 4.0 V, 6.5 V and 8.0 V with 3 dB-voltage bandwidth of 50 GHz, 43 GHz and 41.5 GHz, respectively. All transistors are regular RF MOSFETs with a 1.2 V supply voltage.