Moon-Sig Joo

Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxide-semiconductor flash memory

The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si–SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si–SiO2 interface, are also estimated from the bias voltage dependent DLTS.

Correlation between charge trap distribution and memory characteristics in metal/oxide/nitride/oxide/silicon devices with two different blocking oxides, Al2O3 and SiO2

We examined the origin of the charge traps in bothSiO2/Si3N4/SiO2 (ONO) and Al2O3/Si3N4/SiO2 (ANO) structures and their effect on the memory characteristics by capacitance-voltage (C-V) measurements and deep level transient spectroscopy (DLTS). A larger memory window was observed by C-V for ANO, due to its higher trap density. The DLTS showed that nitride traps are dominant in ANO, while more Si/SiO2 interface-related traps are observed in ONO. The ANO capacitor outperforms the ONO one in terms of both the program efficiency and retention, which is attributed to the reduced number of interface traps in ANO.

Requirements of bipolar switching ReRAM for 1T1R type high density memory array

ReRAM has been researched as a promising candidate for diverse NVM application [1]. Still switching mechanism and classification are not clear, there are simply two kinds of switching polarity: unipolar and bipolar. Considering distribution, operation margin and so on, bipolar switching looks much attractive than unipolar. Along with a selective device, polarity of switching could make the architecture of cell array different. The Crossbar array structure has been considered an attractive solution for unipolar switching with diode. To make the crossbar array with bipolar switching devices, research on a new selective device such as MIEC [2] is much necessary to meet the requirements of current drivability and on/off properties. In addition, self-rectifying device [3–4] could be an alternative for a high density crossbar array. Recently, several research groups have shown very fast and high reliable device. It could be a good signal that ReRAM could have speed and endurance for DRAM or embedded applications. In case of those applications, 1T1R structure could be an effective and it could be used to check the feasibility by changing ReRAM cell with capacitor or MTJ. From now on, transistor has been mainly considered as a controller for the compliance current in set process. But the bipolar 1T1R structure for a high density array, there are several things to be considered, because a transistor would be acting as a changeable resistance at a set and reset process and its resistance goes up as the technology shrinks. So in this paper, we tried to figure out the requirements of bipolar ReRAM switching for the high density 1T1R memory array by changing reset current and symmetry of ReRAM devices.

A comparison between leakage currents in thin gate oxides subjected to X-ray radiation and electrical stress degradation

Abstract Thin gate oxides, irradiated under conditions similar to those experienced in X-ray lithography, exhibit a large increase in the leakage current. The current–voltage characteristics of the radiation-induced leakage current (RILC) and the electrical stress-induced leakage current (SILC) are very similar. Both currents comprise a dc component due to trap-assisted tunneling, and a transient component attributed to the tunnel charging/discharging of carriers. Current–voltage and current–time data suggest essentially the same degradation mechanisms for both the RILC and SILC in ultra-thin oxides. A quadratic relationship between the X-ray dose and the equivalent charge fluence that induces the same amount of degradation is established.

Low Power and Improved Switching Properties of Selector-Less Ta2O5 Based Resistive Random Access Memory Using Ti-Rich TiN Electrode

The effects of TiN top electrode composition (TiN vs Ti-rich TiN) on the resistive switching characteristics of selector-less TiN/TiOx/Ta2O5/TiN resistive random access memory (ReRAM) are investigated. Ti-rich TiN enables TiOx to have a higher concentration of oxygen vacancy and reduce barrier height between top electrode and TiOx. This leads to higher on/off current ratio and lower operation voltage without degradation of non-linearity which is the important factor for selector-less type ReRAM, compared to the stoichiometric TiN resistor stack. Consequently, it is verified that the switching mechanism is hybrid combination of filament formation and redox reaction in switching operation. This work is applicable to both high density and cost-effective ReRAM.

Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.

Effects of Ge Content on the Oxidation Behavior of Poly- Si1 − x Ge x Layers for Gate Electrode Application

Oxidation characteristics of nonpatterned and patterned poly-SiGe layers were evaluated to confirm the feasibility for the application of poly-SiGe to the gate electrode. Characterization of poly-SiGe after oxidation was performed using atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), cross-sectional transmission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy (EDS). The oxide thickness on poly-SiGe layer increased with increasing Ge content, while that on poly-SiGe (Ge 20%) sample was comparable to that of poly-Si (Ge 0%). When the Ge content was more than 40%, two different oxide layers were observed on poly-SiGe. Intensive analyses revealed that the oxide layers were composed of SiO 2 -rich mixed oxide (SiO 2 (GeO 2 )) and GeO 2 -rich mixed oxide (GeO 2 (SiO 2 )). For the patterned poly-SiGe sample, the oxidation characteristics were similar to those of nonpatterned sample. The best sidewall oxide profile was obtained in poly-SiGe (Ge 20%) sample. Because the sidewall oxide thickness is too thick for poly-SiGe sample with more than 40% of Ge, poly-SiGe (Ge 20%) is believed to be the most suitable candidate for gate electrode material.

Thermally Stable NiSi Gate Electrode with TiN Barrier Metal for High-Density NAND Flash Memory Devices

As a gate word line, Ni silicide with a TiN barrier metal has been investigated and demonstrated for NAND flash memory devices with a 24 nm technology node. In addition, physical vapor deposition (PVD) and atomic layer deposition (ALD) TiN layers are compared as diffusion barrier metals. Results show that the carbon impurity in the TiN barrier layer may be one of the factors that affect the quality of the barrier layer at 900 °C. It is also found that Ni diffusion and the discontinuity of Ni silicide induced by the grain growth of polycrystalline silicon (poly-Si) are effectively suppressed by the PVD TiN layer of 20 nm inserted into the control gate. As a result, no significant sheet resistance increase is observed even at a narrow gate line of 24 nm width, and its thermal stability is maintained up to 900 °C.

Diffusion Barrier Characteristics of TiSix/TiN for Tungsten Dual Poly Gate in DRAM

INTRODUCTION Due to the demand of high density and high speed dynamic random access memory (DRAM), gate electrode with a low specific resistance is strongly required to reduce RC delay. For this reason, tungsten polymetal gate could be a good candidate to replace the conventional tungsten polycide gate. However, there are some controversies in choosing an adequate diffusion barrier metal which is crucial for preventing abnormal silicidation between tungsten and poly-Si during post thermal process. In interconnection process, TiN processes are well known to give good characteristics as a diffusion barrier for Al or Cu-based multilevel metallization [1]. Also TiSix/TiN bilayer was reported to show low contact resistance, low stress and flat interface. Recently, some reports have been made for the application of Ti insertion to W poly gate process with a low Rc value [2, 3]. But detailed analysis about interfacial characteristics for the TiSix/TiN diffusion barrier has not been made. Also, dual poly gate processes are strongly required to suppress the short channel effect caused by shortened gate channel length. In p-channel MOSFET, boron penetration into gate oxide could degrade device performance significantly due to flat band voltage shift and increase of interface charge trap density [4, 5]. Increasing the dielectric constant of the top surface gate oxide by plasma nitridation could block boron penetration into gate oxide effectively. However, owing to the high diffusivity of boron in tungsten, it is inevitable for boron to out-diffuse into upper W electrode during thermal processes, which results in severe poly depletion effect. Therefore, inserted barrier metal should also be act as a good barrier which prevents boron from out diffusing into W layer. In this paper, diffusion barrier characteristics of W dual poly gate which involves Ti or TiN were investigated. Barrier characteristic issues relating Ti or TiN inserted gate stack, including gate contact resistance are addressed. The effects of improving p+ poly depletion effect will be shown for W/WN/(TiN)/(Ti)/p+ poly-Si gate stack in detail.

Effects of nitridation pressure on the characteristics of gate dielectrics annealed in N 2 O ambient

Effects of N/sub 2/O pressure during oxynitridation on the characteristics of ultrathin gate dielectrics have been investigated. Reoxidation in N/sub 2/O ambient showed three distinguished oxidation regions as a function of tube pressure; that is, enhancement at 10-40 torr, retardation at 40-100 torr, and enhancement at 100-600 torr. The N/sub 2/O-nitridation at 40 torr incorporated much less nitrogen in oxide bulk than that at near-atmospheric pressure. The 40 torr N/sub 2/O-nitridation case exhibited about 70% of nitrogen incorporation at the Si/SiO/sub 2/ interface compared to that of the 600 torr N/sub 2/O-nitridation case. The low-pressure N/sub 2/O-nitridation at 40 torr results in improvement of TDDB of gate dielectrics and the transconductance of nMOSFETs compared to the nitridation at near-atmospheric pressure. These data suggest that low pressure oxynitridation should be more recommendable for device application.