Seung-Ho Pyi

Analysis of electronic memory traps in the oxide-nitride-oxide structure of a polysilicon-oxide-nitride-oxide-semiconductor flash memory

The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si–SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si–SiO2 interface, are also estimated from the bias voltage dependent DLTS.

Advanced DC-SF Cell Technology for 3-D NAND Flash

Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories.

Characterizations of Pulsed Chemical Vapor Deposited-Tungsten Thin Films for Ultrahigh Aspect Ratio W-Plug Process

Tungsten (W) thin films were deposited using a modified chemical vapor deposition (CVD) process, called pulsed CVD, and the film properties were characterized as nucleation layers for a W-plug fill process. In this study,the deposition stage is composed of four steps, resulting in one deposition cycle: (i) reaction of WF 6 with SiH 4 , (ii) inert gas purge, (iii) SiH 4 exposure, and (iv) inert gas purge. The W growth per cycle was extremely linear with a growth rate of ∼ 1.32 nm/cycle at 400°C. The growth rate was further enhanced to 1.5-1.9 nm/cycle by increasing the SiH 4 flow rate in the first step and/or by adding H 2 in the first and the third steps. The W film deposited by pulsed CVD showed a much lower roughness (∼0.7 nm) and a better conformality at the contact holes with an aspect ratio of 14, compared to W films deposited by conventional CVD using WF 6 and SiH 4 . The film resistivity was closely related with its phase (body-centered cubic α-W or primitive cubic β-W) and microstructure characterized by grain size as well as the film thickness (the size effect). Transmission electron microscopy analysis showed that H 2 addition into the first and third steps increased the grain size from ∼7 to ∼13 nm and prevented the film from forming a β-W phase with high resistivity, resulting in a lower resistivity of 100 Ω-cm compared to that of the W film deposited without H 2 addition (210 μΩ-cm). H 2 addition was also effective in reducing the F and Si impurities in the films. Finally, the film resistivity was discussed on the basis of impurity, roughness, microstructure, and film phase.

Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell

Program disturbance characteristics of 3D vertical NAND Flash cell array architecture have been investigated intensively. A new program Y disturbance mode peculiar to 3D NAND Flash cell is defined. Swing characteristics of poly-Si channel and increased NOP (number of program) stress have been compared with 2D planar NAND Flash cell. In this paper, new program method pertinent to 3D NAND Flash memory was proposed to obtain program disturbance characteristics for MLC.

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.

Pulsed CVD of Tungsten Thin Film as a Nucleation Layer for Tungsten Plug-Fill

Tungsten (W) thin film as a nucleation layer for a W plug-fill process was deposited using a modified chemical vapor deposition (CVD) called pulsed CVD, and properties of the films were investigated. Basically, the deposition stage was composed of four separate steps for one deposition cycle: (i) reaction of WF 6 with SiH 4 ; (ii) inert gas purge; (iii) SiH 4 exposure without WF 6 ; and (iv) inert gas purge. A higher deposition rate, ∼1.5 nm/cycle, was obtained as compared to that of atomic layer deposition (ALD) (∼0.25 nm/cycle). The film deposited by pulsed CVD showed a much lower root mean square (rms) roughness (0.87 nm) and better conformality at the contact holes with an aspect ratio of 14 (contact height: 3.51 μm and top diameter: 240 nm) as compared to the layer deposited by conventional CVD using WF 6 and SiH 4 .

Roles of Ti, TiN, and WN as an Interdiffusion Barrier for Tungsten Dual Polygate Stack in Memory Devices

Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti(N) process were investigated in terms of gate contact resistance (Rc) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSix/TiN bilayer during the postdeposition annealing process. The TiSix reaction between Ti and p+ polycrystalline silicon (poly-Si) effectively prevents the formation of a parasitic dielectric layer, which could lead to low-gate Rc. The TiN reaction between Ti and WN minimizes the occurrence of the TiSix reaction, which effectively reduces p+ polydepletion caused by the out-diffusion of boron during the postdeposition annealing process. Therefore, poly-Si/Ti/WN/W could be a promising tungsten dual polygate stack, which satisfies high-speed requirements in dynamic random-access memory (DRAM) devices.

Observation of Micro-Oxygen Precipitates in the Vicinity of the Oxidation-Induced Stacking Fault Ring and Their Effects on Thin Gate Oxide Breakdown

Micro-oxygen precipitates and their effects on thin gate oxide breakdown have been investigated using a crystal-originated-particle (COP)-free wafer and a low COP wafer. After two-step annealing and subsequent repolishing, regions containing micro-oxygen precipitates were observed inside and outside the oxidation-induced stacking fault (OSF) ring. Delta [Oi] and near-surface microdefects (NSMDs) in those regions showed a reverse trend. It appears that micro-oxygen precipitates show a different precipitation behavior from the anomalous oxygen precipitation (AOP) behavior in the conventional Czochralski (CZ) silicon wafer with the OSF ring. The oxide breakdown electrical field was degraded in almost the same region as that where micro-oxygen precipitates were revealed. This indicates that micro-oxygen precipitates can affect the degradation of gate oxide integrity (GOI).

Limitation of WSix/WN Diffusion Barrier for Tungsten Dual Polymetal Gate Memory Devices

We compared WSix/WN and Ti/WN diffusion barriers for tungsten dual polymetal gate (W-DPG) application, in terms of device performance and gate oxide reliability. WSix/WN diffusion barrier shows degradation of gate oxide, which is found to be due to the B-N dielectric formation and subsequent breakdown of diffusion barrier. Relatively, Ti/WN diffusion barrier shows excellent device performance in terms of R/O delay and gate oxide reliability

Characterization of B2H6 Plasma Doping for Converted p+ Poly‐Si Gate

We have investigated the characteristics of B2H6 plasma doping (PLAD) process used to convert the n+ doped poly‐Si gate to the p+ poly‐Si gate for pMOS. The throughput of the PLAD process is much higher than a conventional beam line implantation process at low energy and high dose ranges. The B2H6 plasma counter‐doping on the n+ poly‐Si were performed in the energy range of 5kV ∼ 9kV and dose of ∼E16♯/cm2. The B2H6 Plasma doped poly‐Si layers were characterized by TDS, SIMS, AFM, and TEM.The TDS analysis showed hydrogen desorption from the B2H6 plasma doped p+ poly‐Si layer at a low temperature. The surface concentration of PLAD doped boron was much higher compared to the conventional beam line implantation. However, a serious loss of surface dopant was also observed during photoresist strip and post cleaning. The surface dopant loss could be suppressed by 10% with optimization of the cleaning condition, leading to improve characteristics of PLAD doped p+ poly‐Si pMOS, compared to the beam line implantati...