Sungki Park

Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application

A novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell has been successfully developed, for the first time. The DC-SF cell consists of a surrounding floating gate with stacked dual control gate. With this structure, high coupling ratio, low voltage cell operation (program: 15V and erase: −11V), and wide P/E window (9.2V) can be obtained. Moreover, negligible FG-FG interference (12mV/V) is achieved due to the control gate shield effect. Then we propose 3D DC-SF NAND flash cell as the most promising candidate for 1Tb and beyond with stacked multi bit FG cell (2 ∼ 4bit/cell).

Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool

Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.

Double patterning of contact array with carbon polymer

The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning technique and double exposure & etch technique (DEET) 1, the former would be preferable to the latter by the issues of overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line & space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact as well as line & space of 30nm half pitch.

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

Effects of CH 2 F 2 Addition on a High Aspect Ratio Contact Hole Etching in a C 4 F 6 / O 2 / Ar Plasma

An SiO 2 contact hole with a diameter of 0.17 μm and an aspect ratio of 15 was etched in C 4 F 6 /O 2 /Ar and C 4 F 6 /O 2 /Ar/CH 2 F 2 plasmas, and the effects of CH 2 F 2 gas on the etch profiles and the etch selectivity to photoresist were investigated. The addition of CH 2 F 2 gas enhanced the production of fluorocarbon films by reactive C-F species, resulting in more fluorocarbon films deposited on the photoresist layer and the sidewalls of the contact hole compared to the CH 2 F 2 gas being absent. This finally led to drastic improvements in the critical dimension loss and the etched contact profiles. The etch selectivity to photoresist was also enhanced in the presence of CH 2 F 2 gas due to hydrogen atoms as well as reactive C-F species. X-ray photoelectron spectroscopy analyses showed that the fluorocarbon films produced in the C 4 F 6 /O 2 /Ar/CΗ 2 F 2 plasma were more carbon-rich compared to those in the C 4 F 6 /O 2 /Ar plasma.

Air-Gap Application and Simulation Results for Low Capacitance in 60nm NAND Flash Memory

In IMD study Rs reduction and better uniformity as well as lower capacitance were achieved in 60 nm 2 Giga Bit NAND flash memory. It alos fabricated 70 % air-gap of gate and calculated interference reduction in 45 nm device when it was applied throughout simulation. It is sure that we should apply this air-gap process to future device in order to meet device property of cell Vt shift and capacitance.

Patterning challenges of EUV lithography for 1X-nm node DRAM and beyond

In this paper, we will discuss patterning challenges of EUV lithography to apply 1xnm node DRAM. EUV lithography is positioned on essential stage because development stage for DRAM is going down sub-20nm technology node. It is time to decide how to make sub-20nm node DRAM. It will be the simplest and cost effective way to make device with matured EUVL. But in spite of world-wide effort to develop EUV lithography, the maturity of EUV technology is still lower than conventional ArF immersion lithography. So, DRAM manufacturers are considering several candidates such as DSA, DPT and MPT simultaneously. In addition, DRAM manufacturers are considering new cell layout and new memory also. For this study, we investigate process window and shadow effect across exposure field of sub-20nm node DRAM cell. We also performed an overlay matching experiment between 0.25NA EUV scanner and 1.35NA ArF immersion scanner. In addition, we will compare EUV lithography with ArF immersion DPT or SPT in view of patterning performance. Finally, we will discuss some technical issues to applying EUV lithography such as flare, resist LER, EUV OPC and illumination condition using 0.25NA EUV scanner.

Requirements of bipolar switching ReRAM for 1T1R type high density memory array

ReRAM has been researched as a promising candidate for diverse NVM application [1]. Still switching mechanism and classification are not clear, there are simply two kinds of switching polarity: unipolar and bipolar. Considering distribution, operation margin and so on, bipolar switching looks much attractive than unipolar. Along with a selective device, polarity of switching could make the architecture of cell array different. The Crossbar array structure has been considered an attractive solution for unipolar switching with diode. To make the crossbar array with bipolar switching devices, research on a new selective device such as MIEC [2] is much necessary to meet the requirements of current drivability and on/off properties. In addition, self-rectifying device [3–4] could be an alternative for a high density crossbar array. Recently, several research groups have shown very fast and high reliable device. It could be a good signal that ReRAM could have speed and endurance for DRAM or embedded applications. In case of those applications, 1T1R structure could be an effective and it could be used to check the feasibility by changing ReRAM cell with capacitor or MTJ. From now on, transistor has been mainly considered as a controller for the compliance current in set process. But the bipolar 1T1R structure for a high density array, there are several things to be considered, because a transistor would be acting as a changeable resistance at a set and reset process and its resistance goes up as the technology shrinks. So in this paper, we tried to figure out the requirements of bipolar ReRAM switching for the high density 1T1R memory array by changing reset current and symmetry of ReRAM devices.

Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRAM

We have investigated the characteristics of cell leakage and data retention time when using flowable oxide chemical vapor deposition (CVD) as a shallow trench isolation (STI) process of 1-Gbit DRAM. The trench gap filling capability was increased dramatically by combining high-density plasma (HDP) CVD with flowable oxide CVD. The reduced local stress by flowable oxide in narrow trenches leaded to decrease in junction leakage and gate induced drain leakage (GIDL) current and increase in data retention time of DRAM compared to HDP STI. Therefore, it is concluded that the combination of flowable oxide and HDP oxide is the most promising technology for STI gap filling process of sub-100 nm DRAM technology.

OPC verification and hotspot management for yield enhancement through layout analysis

As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.