Makoto Furuie

Automatic moving object extraction toward compact video representation

An automatic object-oriented video segmentation and representation algorithm is proposed, where the local variance contrast and the frame difference contrast are jointly exploited for meaningful moving object extraction because these two visual features can indicate the spatial homogeneity of the gray levels and the temporal coherence of the motion fields efficiently. The 2-D entropic thresholding technique and the watershed transformation method are further developed to determine the global feature thresholds adaptively according to the variation of the video components. The obtained video components are first represented by a group of 4x4 blocks coarsely, and then the meaningful moving objects are generated by an iterative region-merging procedure according to the spatiotemporal similarity measure. The temporal tracking procedure is further proposed to obtain more semantic moving objects and to establish the correspondence of the moving objects among frames. Therefore, the proposed automatic moving object extraction algorithm can detect the appearance of new objects as well as the disappearance of existing objects efficiently because the correspondence of the video objects among frames is also established. Moreover, an object-oriented video representation and indexing approach is suggested, where both the operation of the camera (i.e., change of the viewpoint) and the birth or death of the individual objects are exploited to detect the breakpoints of the video data and to select the key frames adaptively.

Realtime wavelet video coder based on reduced memory accessing

In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die.

Parasitic capacitance modeling for multilevel interconnects

The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be represented by a simple expression adjusted to the results computed by an electromagnetic field solver based on a two-dimensional capacitance model. An approximate expression of the total capacitance between two crossing interconnects is obtained by summing the capacitances in all regions. In order to evaluate the accuracy of this approximation, the capacitance calculated by the attained expression is compared with the one obtained by a three-dimensional field solver, and it turns out that the error is less than 5%.

Two-dimensional array layout for NMOS 4-phase dynamic logic

A novel layout approach of array cell (AC) architecture is described, which is dedicated to nMOS 4-phase dynamic logic. An AC is constructed of (M/spl times/N)+2 nMOSFETs which constitute each type of nMOS 4-phase logic gates. A graph theoretic approach to the nMOSFET placement in conjunction with a simulated annealing procedure is exploited for the area reduction in the layout design of the AC. A number of experimental results demonstrate the practicability of the proposed approach.

Layout generation of array cell for NMOS 4-phase dynamic logic

An array cell (AC) architecture for the layout design is described, which is dedicated to low-power design by means of NMOS 4-phase dynamic logic. An AC is constructed of (M/spl times/N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. A graph theoretic approach is exploited in the layout design to reduce the layout area. A number of experimental results demonstrate the practicability of the proposed approach.

Layout generation of array cell for NMOS 4-phase dynamic logic (short paper)

| An array cell (AC) architecture for the layout design is described, which is dedicated to lowpower design by means of the NMOS 4-phase dynamic logic. An AC is constructed of (M N)+2 transistors so as to constitute each type of NMOS 4-phase logic gates. A graph theoretic approach is exploited in the layout design to reduce the layout area. A number of experimental results demonstrate the practicability of the proposed approach.

Layout generation for low-power NMOS 4-phase dynamic logic array

An array cell (AC) architecture is described, which is dedicated to low-power design of NMOS 4-phase dynamic logic. This AC is constructed of (M/spl times/N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. The structure regularity of the AC contributes much toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the NMOS 4-phase dynamic logic.