Inka Zienert

Analytics and Metrology of Strained Silicon Structures by Raman and Nano‐Raman Spectroscopy

Straining the active regions in MOSFET devices is one of the key contributors to increase device performance in present and future technology nodes. Since dedicated strain on the transistor level is required with opposite sign for NMOS and PMOS transistors, the need to measure strain locally has become a challenge for analytics and metrology. Raman spectroscopy is capable of obtaining strain information non‐destructively on the sub‐μm scale, and therefore, this technique has been considered for process monitoring. In this paper it will be shown for silicon‐germanium thin films, how both strain and composition can be determined independently by measuring two phonon modes of the film. This technique enables fast measurement of mechanical strain and chemical composition with high accuracy on the μm‐scale. Thus, the micro‐Raman technique is well suited for metrology of strained silicon test structures. Furthermore, it is shown that mechanical strain close to silicon‐germanium structures can be measured with n...

Electron Backscatter Diffraction: Application to Cu Interconnects in Top-View and Cross Section

EBSD has been applied to study the microstructure of copper interconnects in detail. Both, top-view and cross-section investigations were performed. FIB polishing was successfully applied to obtain cross-sections of specific structures like vias. Moreover, it has been shown that passivated test structures can be investigated. With the high spatial resolution of EBSD it also becomes possible to study nanointerconnects with critical dimension of 60 nm and below. Complex experiments can be conducted, which will improve the understanding of the microstructure evolution and the impact on performance and reliability of advanced integrated circuits.

Process Control and Physical Failure Analysis for Sub-100NM CU/Low-K Structures

For successfully developing and controlling BEoL structures of the 32 nm CMOS technology node and beyond, advanced analytical techniques are needed for process development and control, for physical failure localization and analysis as well as for the investigation of reliability-limiting degradation mechanisms. These challenges are discussed from the point of view of a high volume leading-edge manufacturing.

Texture and Stress Study of Sub-Micron Copper Interconnect Lines Using X-ray Microdiffraction

In addition to standard reliability tests, both a careful process control based on a large number of data to reach statistically relevant conclusions and the study of solid-state physical degradation mechanisms at representative samples are needed to understand weaknesses in the interconnect technology and to exclude reliability-related failures in copper interconnects. In addition, numerical simulation will help forecast the effect of process and material changes on interconnect reliability.

Potential and Limits of Texture Measurement Techniques for Inlaid Copper Process Optimization

For future technology nodes with shrunken interconnect dimensions, a thorough texture analysis of the metal interconnects becomes increasingly important in order to optimize and to control the inlaid‐copper process. In comparison to plane metal layers deposited on wafers, the microstructure of the metal is more complicated in copper lines and vias which were produced using an inlaid process. Therefore, advanced texture‐measurement techniques like X‐ray microdiffraction, electron backscatter diffraction (EBSD), and TEM combined with automated crystallography analysis (ACT) are needed to obtain the required microstructure information. These complementary methods are suitable to pick up local as well as integral information on the crystallographic orientation of the copper interconnects and liner materials. Potential and limits of the available techniques and the respective instrumentation are discussed in this paper. Examples of process‐monitoring capabilities and of development support, especially with reg...

Temperature‐Dependent Stress Measurements at Inlaid Copper Interconnect Lines

The 3‐dimensional stress state of inlaid copper line structures in low‐k dielectrics was measured using synchrotron micro X‐ray diffraction (μ‐XRD) at temperatures between 25°C and 450°C. The barrier layer (Ta or TaN/Ta) had only a low impact on the stress‐temperature behaviour. However, an additional thick SiOxFy capping layer lowered the room temperature stress significantly compared to copper lines with a thin SiCxNy passivation. The effect of this thick capping layer on the slope of the stress‐temperature curve was even more dramatic. Samples without a thick SiOxFy capping layer showed a transition from in‐plane tensile stress to compressive stress between 150°C and 250°C, while samples capped with thick SiOxFy reached this point at higher temperatures or in some cases even stayed tensile up to 400°C. This shift was also dependent on the copper line width. Furthermore, in 4μm wide lines with thick SiOxFy cap the out‐of‐plane stress became more tensile with increasing temperature, leading to a reverse ...

Microstructure Effect on Electromigration‐Induced Degradation of Inlaid Copper Interconnects

Electromigration‐induced degradation processes in via/line dual inlaid copper interconnect test structures are discussed based on experimental studies. Void formation, growth and movement, and consequently interconnect degradation, depend on both interface bonding and copper microstructure. Void movement along the copper line and void growth in the via are discontinous processes, wherein their step‐like behavior is caused by copper microstructure. Microstructure studies and microstructure monitoring are becoming more important for strengthened top interfaces of copper lines, e. g. by local alloying of the copper or by applying an additional coating on top of the polished copper lines. As a result of this interface engineering, the contribution of grain boundary diffusion becomes increasingly important for the directed mass transport and for electromigration‐induced degradation.

The Evolution of Barrier Properties During Reliability Testing of Cu Interconnects

The investigation of stress‐induced voiding (SIV) is one of the key aspects to characterize metallization reliability. Typical test methodologies include the investigation of resistance shifts during temperature storage tests at temperatures between 150° C to 275° C. During these tests, only very small resistance increases dependent on the test structure are allowed. Physical failure analysis of such samples typically reveals voids below the vias of the test structures. However, recently we encountered unusual resistance shifts at the highest stress temperature which did not yield classical stress‐induced voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.

Electromigration-induced copper interconnect degradation and failure: the role of microstructure

In this paper, EM-induced degradation processes and failure in on-chip interconnects are discussed based on experimental studies. In-situ microscopy studies at embedded via/line dual inlaid copper interconnect test structures show that void formation and evolution depend on both interface bonding and microstructure. In future, copper microstructure becomes more critical for interconnect reliability since grain boundary diffusion becomes increasingly important for structures with strengthened interfaces, i. e. interfaces are the fastest pathways for the EM-induced mass transport any more. Particularly, grain boundaries have to be considered as significant pathways for mass transport in copper interconnects.

Micro-XRD Stress And Texture Study Of Inlaid Copper Lines - Influence Of ILD, Liner And Etch Stop Layer

The influence of ILD, liner and etch stop layer on the room temperature stress state of copper line test structures was examined by micro‐XRD. Test structures consisted of large arrays of parallel lines with line widths of 0.18 μm and 1.8 μm. All these parameters have an influence on the room temperature stress state, whereas the variation of the liner and the ILD showed the largest effects. The change from a full low‐k stack to a hybrid stack, where SiO2 ILD is use for the ‘via layer’ only and low‐k material for the ‘line layer’ results in completely different parameter dependencies. The relationship between copper microstructure and the resulting stress in copper lines is discussed.