Akio Toda

Local lattice strain distribution around a transistor channel in metal–oxide–semiconductor devices

The local lattice strain around the channel in metal–oxide–semiconductor (MOS) field-effect transistors of 0.1 μm gate length was measured by using convergent-beam electron diffraction. It was found that the normal strain along the gate-length direction is compressive beneath the gate and is larger for devices having smaller diffusion sizes in the gate length direction L′. The drive current Ion decreased for an n-channel MOS and increased for a p-channel MOS as L′ decreased. These results are consistent with those of a previous study. However, our results also revealed that the strain distribution around the channel region was strongly affected not only by the stress from the shallow trench isolation but also by the device structures around the gate.

PZT MIM capacitor with oxygen-doped Ru-electrodes for embedded FeRAM devices

An add-on-type, Pb(Zr,Ti)O/sub 3/ (PZT) metal-insulator- (MIM) capacitor on Al multilevel interconnects is developed for embedded FeRAM devices, concluding that the oxygen-doping into the ruthenium (Ru) electrodes is crucial for obtaining large remnant polarization under a limited process temperature below 450/spl deg/C. The oxygen-doped, Ru bottom-electrode with a granular structure reduces the PZT sputtering temperature below 450/spl deg/C to obtain the ferroelectric perovskite-phase. On the other hand, oxygen doping into the Ru top-electrode suppresses the reductive damage at the interface between the top-electrode and the PZT, keeping the leakage current low. The PZT MIM capacitor with these oxygen-doped, Ru electrodes exhibits the remnant polarization of 21 /spl mu/C/cm/sup 2/ on the Al multilevel interconnects with no degradation of the interconnect reliability, thus applicable to the embedded FeRAM in 0.25 /spl mu/m-CMOS logic LSIs.

Electron holography for analysis of deep submicron devices: Present status and challenges

A potential distribution analysis of source/drain (SD) regions in sub-30-nm-gate-length metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented as an example of the present status of electron holography analysis. First, the authors describe experimental setups that determine the resolutions of the analysis in practice. They show that specimen preparation artifacts significantly affect the energy resolution and that the artifacts can be reduced by preparing specimens using low-energy back side ion milling. Second, they describe the SD potential analysis in sub-30-nm-gate-length MOSFETs.

Determining the relationship between local lattice strain and slip systems of dislocations around shallow trench isolation by convergent-beam electron diffraction

We clarified the generation of process-induced dislocations around a shallow trench isolation (STI) by using convergent-beam electron diffraction. Comparing the resolved shear strain (RSS) of 12 slip systems, we found that at the trench bottom corner the RSS on slip systems (1 −1 1)[0 1 1] and (1 −1 1)[1 0 −1] was largest in all slip systems. In fact, the dislocations of slip systems (1 −1 1)[0 1 1] and (1 −1 1)[1 0 −1] were observed around the trench bottom corner more often than those of any other slip systems. We also found that the large RSS at the trench bottom corner may be due to the corner shape or the intrinsic stress induced during oxidation. Therefore, to control dislocation around STI, the oxidation-induced stress at the trench bottom corner must be reduced, and the shape of the bottom corner must be controlled.

Channel Strain in Advanced Complementary Metal–Oxide–Semiconductor Field Effect Transistors Measured Using Nano-Beam Electron Diffraction

Using high-precision nano-beam electron diffraction (NBD), we clarified the influences of stress liner and the stress of shallow trench isolation on channel strain in advanced metal–oxide–semiconductor field effect transistors (MOSFETs). For systematic strain measurements, we improved the precision of NBD by observing large reciprocal lattice vectors under appropriate diffraction conditions. The absolute value of the channel strain increases by stress liner as gate length decreases, although the drive current increase due to stress liner saturates at a shorter channel length. The normal strain in the gate length direction is inversely proportional to the distance from the gate electrode to the shallow trench isolation (STI). Furthermore, the relationship between measured channel strain induced by STI and drive current change was shown. The drive current of n- and p-MOSFET changes about 5% with 2×10-3 channel strain variation. This result suggests that reducing the shallow trench isolation stress is effective for controlling the drive current change, depending on the active region layout. We conclude that the experimental measurement of channel strain is necessary for device and circuit design.

Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit

We investigated electrostatic potential distributions in source∕drain extensions (SDEs) in metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated using state-of-the-art junction formation technology. We first demonstrate that electron holography can directly reveal potential distribution in scaled MOSFETs when specimen preparation artifacts are reduced, which we did by using back side low-energy Ar ion milling. Second, we examine the potential distributions in SDEs in a scaled (30‐nm-gate-length) MOSFET fabricated by using a combination of cluster B implantation, millisecond annealing, and multihalo implantation. The results show that these junction formation technologies enable fabrication of very abrupt and shallow (10‐nm-deep) SDE junctions. In addition, our experimental analysis, in conjunction with a Monte Carlo doping-process simulation, indicates that B channeling along the ⟨110⟩ direction of the Si substrate during the implantation process significantly blurs the SD junction profi...

Impact of mechanical stress on interface trap generation in Flash EEPROMs

We show that the compressive mechanical stress in the channel of a Flash EEPROM cell degrades data retention characteristics through the generation and recovery of traps at the tunnel-oxide/Si substrate interface. To demonstrate this, we measured the mechanical stress and interface trap density in 0.15 /spl mu/m-rule NOR cells using convergent-beam electron diffraction and charge pumping methods. Hydrogen atoms, another possible factor, had less influence than mechanical stress.

Nondestructive Warpage Measurements of LSI Chips in a Stacked System in Package by Using High-Energy X-ray Diffraction

We describe high-energy X-ray diffraction to examine the warpage of packaged LSI chips nondestructively. Less absorption of the high-energy X-rays enables us to observe diffracted X-rays through packaging materials and LSI chips. We demonstrate that it is possible to measure the warpage of LSI chips in a stacked system in package (SiP). Although an LSI chip in a single-chip ball grid array (BGA) package simply warps into a convex-down shape, the LSI chips packaged in the BGA package as a stacked SiP warp into the shape of waves. It is inferred from results of our examination that the stress due to a printed circuit board substrate and molding resin affects chip warpage.

Higher-order Laue zone line contrast in large-angle convergent-beam electron diffraction around a dislocation.

The physical picture of higher‐order Laue zone (HOLZ) line contrast in a large‐angle convergent‐beam electron diffraction pattern around a dislocation, which is used for determining the Burgers vector, was examined. To evaluate the analytical expression of diffracted wave amplitude, we introduced an approximate form of the atomic displacement field of a dislocation. We showed that the four features of the HOLZ line contrast, that is, splitting, fading, bending and periodical contrast can be explained by analysis of the atomic displacement field. The localized lattice plane bending around a dislocation core made a HOLZ line split, fade and bend. However, we found that the periodical contrast of a HOLZ line was produced by the change of phase difference of the atomic displacement field between the crystals above and below the slip plane across the dislocation line.

Impact of Crystalline Phase of Ni-FUSI Gate Electrode on Bias Temperature Instability and Gate Dielectric Breakdown of HfSiON MOSFETs

We investigated the influences of gate metals (n+/p+ poly-Si, Ni silicide (NiSi), Ni3Si) on the time dependent dielectric breakdown (TDDB) reliability and negative/positive bias temperature instability (NBTI/PBTI) of phase-controlled Ni-full-silicide (Ni-FUSI)/HfSiON/SiO 2 FETs. The TDDB reliability of NiSi-electrode n-FETs was comparable to that of n+-poly-Si-electrode n-FETs. However, further Ni enriching of the electrode to Ni3Si degraded the reliability. A degradation of the base SiO2 layer seems to have been responsible for this. A higher compressive strain was observed for the Ni3Si sample, which may have caused the degradation of the bottom SiO2. In contrast, the TDDB reliability of p-FETs improved much by using Ni3Si. We attribute this improvement to the lower cathode energy and/or the absence of boron in the gate electrode. The PBTI of the n-FETs was negligible and was not degraded by Ni enrichment of the gate electrode and additional annealing, suggesting that HfSiON was stable against the Ni-FUSI process. The threshold voltage (VT) shift in NBTI of p-FETs did not depend much on the gate materials. The major component of the V T shift in NBTI, however, was changed by Ni enriching from the generation of interface traps to the trapping of holes by the HfSiON bulk