Nobuyuki Ikarashi

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

We present a new threshold-voltage (Vth) control technique for fully-silicided (FUSI) metal/high-k gate stacks which are suitable for 45nm-node LOP and LSTP CMOS. The key is the phase control of FUSI Ni-silicide by changing Ni film thickness prior to silicidation anneal. As a result, Ni/sub 3/Si and NiSi/sub 2/ are formed whose effective workfunctions (WFs) on HfSiON are found to be 4.8eV and 4.4eV, respectively, being largely displaced from Si-midgap by /spl plusmn/0.2eV. Meanwhile, the dopant segregation method, known to be successful in Vth-control of NiSi on SiO/sub 2/, did not work on HfSiON. With Ni/sub 3/Si-PMOS and NiSi/sub 2/-NMOS transistors, a wide range of Vth-tuning is achieved coping with both LSTP and LOP requirements. At the same time, leakage suppression merit is better than the 45nm-node targets at electrical thickness (Tinv) around 2.0 nm. Also, our phase-controlled fully silicided (PC-FUSI) devices show excellent mobility characteristics.

Thermal decomposition of ZrO2/SiO2 bilayer on Si(001) caused by void nucleation and its lateral growth

The stability of a ZrO2/SiO2 bilayer on a Si(001) substrate was investigated in terms of thermal decomposition during ultrahigh-vacuum annealing. In spite of the intrinsic thermal stability of the ZrO2/SiO2 system, void nucleation initiated by local defects and the following lateral growth of the voids proceed at temperatures over 900 °C. The remaining Zr atoms accumulate and react with the Si substrate to form silicide (ZrSi2) islands within the voids. It was found that the decomposition temperature of the ZrO2/SiO2 bilayer is lower than that of a SiO2 single layer, which suggests defect generation in the SiO2 underlayer by ZrO2 deposition.

ANALYTICAL TRANSMISSION ELECTRON MICROSCOPY OF HYDROGEN-INDUCED DEGRADATION IN FERROELECTRIC PB(ZR, TI)O3 ON A PT ELECTRODE

Changes in the crystal structure of Pb(Zr, Ti)O3 (PZT) on a Pt electrode caused by annealing in hydrogen-containing ambient have been studied using analytical transmission electron microscopy. A decrease in Pb composition and distortion in Ti–O coordination occur at the PZT/Pt interface. These findings indicate that preferential reduction of Pb and sequential diffusion of Pb from the PZT to the Pt electrode play an important role in the changes of the PZT crystal. Thus, changes in crystal structure due to annealing in a hydrogen-containing ambient can be avoided by using electrode materials that prevent Pb diffusion.

Electronic structure analysis of Zr silicate and Hf silicate films by using spatially resolved valence electron energy-loss spectroscopy

Electronic structures near the band gaps of Zr silicate and Hf silicate thin films were investigated experimentally and theoretically. We show that the electronic structure of Zr silicate can be reproduced by a superposition of the electronic structures of ZrO2 and SiO2. Similarly, the electronic structure of Hf silicate can be reproduced by a superposition of the electronic structures of HfO2 and SiO2. This indicates that, in these silicates, the lowest conduction band states are composed mostly of d states of Zr or Hf, and the valence band states mostly of O 2p states. The similarity of the electronic structures of these silicates can be attributed to the similarity of the chemical natures of Zr and Hf atoms. Consequently, when these silicate films are used as gate dielectrics in metal–oxide–semiconductor transistors, the gate leakage current could be strongly affected by d states of Zr or Hf.

La–silicate gate dielectrics fabricated by solid phase reaction between La metal and SiO2 underlayers

La-based high-k gate dielectrics were fabricated by reoxidation of thin La layers deposited on SiO2 underlayers. Interface reaction that causes metal diffusion through the oxide underlayer increases permittivity of the oxide and forms high-quality La–silicate films. We successfully fabricated ultrathin La–silicates of equivalent oxide thickness ranging from 0.75 to 1.6 nm with low-leakage current by controlling the interface solid phase reaction. We characterized degradation in the silicate film caused by electrical stressing and demonstrated the effectiveness of high-temperature annealing to improve the reliability of silicate dielectrics. Moreover, it was found that water absorption during exposure to air causes positive fixed charge in the silicate (flatband voltage shift), but degradation can be annealed out at relatively low temperatures.

High-quality HfSixOy gate dielectrics fabricated by solid phase interface reaction between physical-vapor-deposited metal–Hf and SiO2 underlayer

We fabricated high-quality Hf–silicate (HfSixOy) gate dielectrics by utilizing the solid phase interface reaction between physical-vapor-deposited metal–Hf (typically 0.5nm thick) and SiO2 underlayers. Metal diffusion to the SiO2 layer increases the permittivity of the underlayer, while preservation of the initial SiO2∕Si bottom interface ensures good electrical properties of the gate dielectrics. The Hf–silicate layer remains amorphous and the poly-Si∕HfSixOy gate stack endures activation annealing at 1000°C. The interface trap density was comparable to that of conventional SiO2 dielectrics and the hysteresis of capacitance–voltage curves was as low as 4mV for a bias swing between −2 and +2.5V. Moreover, high electron mobility, equal to 89% of the universal mobility, was obtained for the high-k gate transistor.

Effects of Ti addition on via reliability in Cu dual damascene interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.

Local lattice strain distribution around a transistor channel in metal–oxide–semiconductor devices

The local lattice strain around the channel in metal–oxide–semiconductor (MOS) field-effect transistors of 0.1 μm gate length was measured by using convergent-beam electron diffraction. It was found that the normal strain along the gate-length direction is compressive beneath the gate and is larger for devices having smaller diffusion sizes in the gate length direction L′. The drive current Ion decreased for an n-channel MOS and increased for a p-channel MOS as L′ decreased. These results are consistent with those of a previous study. However, our results also revealed that the strain distribution around the channel region was strongly affected not only by the stress from the shallow trench isolation but also by the device structures around the gate.

High‐resolution electron microscopy of growth interruption effect on AlAs/GaAs interfacial structure during molecular beam epitaxy

Step structures at an AlAs/GaAs interface grown by molecular beam epitaxy (MBE) and the effects of growth interruption were investigated by high‐resolution transmission electron microscopy (HRTEM) of the interface in the [110] imaging orientation. In order to accomplish this, we developed a new TEM specimen preparation technique and determined an observation condition for HRTEM of the interface. Atomic steps were clearly observed at the AlAs‐on‐GaAs interface grown by conventional MBE, and the step intervals ranged from a few nm to several tens of nm. When 120 s growth interruption was employed, the interfacial steps were smoothed out and the step intervals become larger than several tens of nm.

Formation mechanism of interfacial Si–oxide layers during postannealing of Ta2O5/Si

The Si–O–Si bonds formed at the Ta2O5/Si interface by annealing were investigated by using Fourier transform infrared absorption spectroscopy. The Ta2O5 thin films deposited on Si substrates were annealed in different ambient (H2O, O2, and N2) at temperatures between 500 and 800 °C. When annealing is done in H2O, the interfacial silicon–oxide grows very rapidly, because the oxidation species can easily diffuse through Ta2O5 films, and because the Si–O formation is controlled by the diffusion of H2O in the interfacial layer. When annealing is done in O2, the oxidation species can also easily diffuse through Ta2O5, but not through the interfacial layer. The interfacial layer is formed by a reaction between Ta2O5 and Si even if the annealing ambient does not contain oxidation species, as is the case when annealing is done in N2. We conclude that the Si–O formation during postannealing in O2 and N2 is controlled by the diffusion of the Si from the substrate through the interfacial layer with an activation ene...