Motoshu Miyajima

Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7- µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

This paper presents a 65 nm CMOS technology for mobile multimedia applications. The reduction of interconnect capacitance is essential for high-speed data transmission and small power consumption for mobile core chips. We have chosen a hybrid ULK structure which consists of NCS (nano-clustering silica; k=2.25) at the wire level and SiOC (k=2.9) at the via level. Although NCS is a porous material, the NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bonding. Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistors meet the electrical targets from the circuit requirements. Moreover, an embedded 6T-SRAM with a 0.55 /spl mu/m/sup 2/ small cell size has been achieved.

45 nm-node BEOL integration featuring porous-ultra-low-k/Cu multilevel interconnects

45 nm-node multilevel Cu interconnects with porous-ultra-low-k have successfully been integrated. Key features to realize 45 nm-node interconnects are as follows: 1) porous ultra-low-k material NCS (nano-clustering silica) has been applied to both wire-level and via-level dielectrics (what we call full-NCS structure), and its sufficient robustness has been demonstrated; 2) 70-nm vias have been formed by high-NA 193 nm lithography with fine-tuned model-based OPC and multi-hard-mask dual-damascene process - more than 90% yields of 1 M via chains have been obtained; 3) good TDDB (time-dependent dielectric breakdown) characteristics of 70 nm wire spacing filled with NCS has been achieved. Because it is considered that the applied-voltage (Vdd) of a 45 nm-node technology will be almost the same as that of the previous technology, the dielectrics have to endure the high electrical field. NCS in Cu wiring has excellent insulating properties without any pore sealing materials which cause either the k/sub eff/ value or actual wire width to be worse.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

Investigation of stress-induced voiding inside and under VIAS in copper interconnects with “wing” pattern

Stress induce voiding (SIV) inside and under vias in copper interconnects with ldquowingrdquo-pattern were investigated for 90 nm and 65 nm node processes. The difference of two voidings are the resistance change during acceleration test and the diffusion path. However, common features were found between both types of voiding; the interconnect fails fast as the ldquowingrdquo area grows. Both types of voiding have a critical ldquowingrdquo area where failure never occurs. Both of voiding is more affected by diffusion source than by stress gradient.

0.65 V device design with high-performance and high-density 100 nm CMOS technology for low operation power application

A low-power, high-speed and high-density 100 nm CMOS technology is developed for very-low-voltage (Vds=0.65 V) operation by using ArF 193 nm lithography, high-performance transistors with sidewall notch, high-density SRAM cell (1.16 /spl mu/m/sup 2/) and copper (Cu) and very-low-k (VLK) interconnect (k/sub eff/=3). For reduction of power consumption and improvement of circuit speed in dynamic operation, high-current transistors at low voltage, interconnect with VLK dielectrics and transistors with reduced parasitic capacitance are required. High-performance transistors with sidewall notch to reduce overlap and junction capacitance and Cu/VLK interconnect with low-k SiC barriers realize higher circuit speed by 10% and lower power consumption by 80%, compared to 130 nm CMOS technology.

On the Elements of High Throughput Cu-CMP Slurries Compatible with Low Step Heights

In order to achieve high throughput Cu-CMP compatible with low step heights in 32nm Node copper interconnect technologies and beyond, we believe it is crucial a passivation layer on the Cu surface in the slurry during the CMP process. We show that the formation of a passivation layer which achieves good planarization with high Cu removal rate can be controlled by selecting the rest potential of the Cu ions in the slurry.

Suppression of Defect Formation and Their Impact on Short Channel Effects and Drivability of pMOSFET with SiGe Source/Drain

The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step, the initial defect density is reduced, and by introducing a cap layer on a SiGe layer, the thermal stability of the SiGe layer is improved. The optimized devices enhance mobility 42% by maximizing the strain effect and provide better SCE characteristics by suppressing boron diffusion

A highly reliable nano-clustering silica with low dielectric constant (k<2.3) and high elastic modulus (E=10 GPa) for copper damascene process

A highly reliable nano-clustering silica (NCS) with low dielectric constant(k<2.3) and high elastic modulus (E=10 Gpa) for copper damascene process has been developed by controlling the size and distribution of pores in the NCS precursor. Using this material in a process compatible with the 90 nm technology node, we successfully demonstrated Cu wiring in NCS dielectrics.

Cu interconnect technologies in Fujitsu and problems in installing Cu equipment in an existing semiconductor manufacturing line

Summary form only given. In this paper, Cu interconnect technologies in Fujitsu targeted for the 0.18 /spl mu/m generation and beyond are introduced. Some new integration schemes for Cu wiring are also demonstrated, targeted for the 0.13 /spl mu/m generation. Finally, we discuss some important aspects of installation of Cu equipment in an existing semiconductor manufacturing line.