Mu-Shih Yeh

The growth behavior of Pb0.95La0.05(Zr0.7Ti0.3)0.9875O3 films on silicon substrates synthesized by pulsed laser deposition

The highly (110) textured Pb0.95La0.05(Zr0.7Ti0.3)0.9875O3 (PLZT) films have been successfully grown on SrTiO3(STO)‐buffered silicon substrates. The films, deposited by pulsed laser deposition process, are assumed to form via a two‐step process, i.e., cluster adherence and phase transformation. The beneficial effect of using STO as buffer layers involves enhancing the kinetics of phase transformation from amorphous phase to perovskite. The loss of Pb species from the films is thereby suppressed. The optimum dielectric constants obtained are around er=490 for PLZT/STO/Si films deposited at 550 °C (1 mbar oxygen pressure, PO2) and post‐annealed at 550 °C (1 atm PO2). The corresponding charge storage density is around Qc≂1.5 μC/cm2 at 50 kV/cm applied field strength.

SrTiO3 buffering effect on Pb1-xLaxTiO3 thin films prepared by pulsed laser deposition

Thin films of phase‐pure perovskite PLT (Pb0.95La0.05Ti0.9875O3) were deposited in situ onto Si, Pt/Ti/SiO2/Si, and SrTiO3/Si substrates by pulsed laser deposition from stoichiometric targets. No Pb loss was observed in the near‐surface region. The blocking of the interdiffusion between inner Si substrate and the outer PLT films by SrTiO3 buffer layer was evidenced using x‐ray diffraction (XRD) and secondary ion mass spectrometry (SIMS) analyses. The formation of TiO2 second phase in PLT/Pt/Ti/SiO2/Si films was indicated by XRD and SIMS spectra to be the outward diffusion of Ti atoms from the underlying Ti layer through the Pt layer, reacting with ambient O2 at the PLT‐to‐Pt interface.

Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure

Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness (TCH) and gate length (LG). These devices (LG = 0.5 μm) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high ION/IOFF current ratio (106A/A) and practically negligible drain-induced barrier lowering (~0 mV/V). The ION current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications.

High-Performance Gate-All-Around Poly-Si Thin-Film Transistors by Microwave Annealing With NH

This paper introduces nanoscale gate-all-around (GAA) n-MOS polycrystalline silicon thin-film transistors (poly-Si TFTs) by using microwave annealing (MWA). Experimental results of MWA GAA poly-Si TFTs indicate high performances with subthreshold swing (SS) of 105 mV/dec., and ION/IOFF ratio of 107 A/A. MWA reveals sufficient dopant activation efficiency, which is equivalent to rapid thermal annealing. Additionally, the short channel effect is reduced owing to the low-temperature process of MWA and superior gate control of the GAA structure. Moreover, using NH3 plasma treatment further improves the device mobility, ION/IOFF ratio, and SS. Importantly, the proposed MWA GAA poly-Si TFT with its high performance and low-temperature process is highly promising for advanced 3-D ICs.

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This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

Plasma Passivation

Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length (λ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage (VBTBT) indicates clearly that TFET annealed by MWA had a lower λ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of 108, a low subthreshold swing, and an almost negligible drain-induced barrier lowering.

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory

The novel trench junctionless poly-Si thin-film transistor (trench JL-TFT) with ultra-thin body (2.4 nm) is utilized to simple dry etching process. This novel devices show excellent performance in terms of steep SS (99 mV/dec.) and high I_ON/I_OFF (>10⁷). The I_ON current of the ultra-thin body (UTB) JL-TFT is increased by quantum confined effect.

Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor

This work presents p-channel and n-channel junctionless (JL) polycrystalline silicon (poly-Si) nanowires gate-all-around (GAA) nonvolatile memory (NVM) devices with silicon nanocrystals charge trapping layer. Experimental results indicate that the n-channel device has better programming efficiency and p-channel device has better erasing efficiency. For p-channel device, an extrapolation of the memory window to 10 yr demonstrates that 95% of the stored charge can be retained at high temperature of 85 °C. Such the p-channel and n-channel JL-GAA NVMs are feasible for use in system-on-panel (SOP) and 3-D stacked flash memory applications.

High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure

Thin films of (Pb1−xLax)(Zr1−yTiy)1−x/4O3 (5/70/30) were deposited in situ onto (100) Si, Pt/Ti/SiO2/Si, and SrTiO3/Si substrates by pulsed laser deposition from stoichiometric targets and subsequent annealing. Films grown on SrTiO3/Si exhibited desired perovskite structure. On (100) Si and Pt/Ti/SiO2/Si substrates, films exhibited a perovskite‐pyrochlore mixed structure. Apparent Pb deficiency at the near‐surface region was observed. Films deposited at different substrates showed variations in Si content. The buffering effect of SrTiO3 was evidenced using x‐ray diffraction and secondary ion mass spectrometry analyses.

Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory

This paper demonstrates a silicon-oxide-nitrideoxide-silicon (SONOS) nonvolatile memory (NVM) with fin-shaped polycrystalline silicon channel tunnel field-effect transistor (TFET). It differs from other memory devices in that its programming mechanisms include Fowler-Nordheim (FN) tunneling, channel hot-electron (CHE) injection, and band-toband tunneling-induced hot electron (BBHE) in single memory cell. In FN programming, both the ON-state current and the program/erase (P/E) operations are based on quantum tunneling. For FN tunneling, when a VG of 17 V is applied for only 1 ms, this device has a large threshold voltage shift (ΔVTH) of 4.7 V. The fin-shaped TFET SONOS (T-SONOS) NVM exhibits superior endurance of 88% after 104 P/E cycles. The memory window remains 65% of its original value after 10 years at a high temperature of 85 °C. On the other hand, the device exhibits better endurance of 74% for CHE programming and BBHE programming after 104 P/E cycles. The memory window retains 81% in CHE programming and 65% in BBHE programming after 10 years. The fin-shaped T-SONOS NVM exhibits high performance that can be achieved in polycrystalline silicon NVM.