Min-Hsin Wu

Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure

Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness (TCH) and gate length (LG). These devices (LG = 0.5 μm) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high ION/IOFF current ratio (106A/A) and practically negligible drain-induced barrier lowering (~0 mV/V). The ION current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications.

High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure

The novel trench junctionless poly-Si thin-film transistor (trench JL-TFT) with ultra-thin body (2.4 nm) is utilized to simple dry etching process. This novel devices show excellent performance in terms of steep SS (99 mV/dec.) and high I_ON/I_OFF (>10⁷). The I_ON current of the ultra-thin body (UTB) JL-TFT is increased by quantum confined effect.

Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory

This work presents p-channel and n-channel junctionless (JL) polycrystalline silicon (poly-Si) nanowires gate-all-around (GAA) nonvolatile memory (NVM) devices with silicon nanocrystals charge trapping layer. Experimental results indicate that the n-channel device has better programming efficiency and p-channel device has better erasing efficiency. For p-channel device, an extrapolation of the memory window to 10 yr demonstrates that 95% of the stored charge can be retained at high temperature of 85 °C. Such the p-channel and n-channel JL-GAA NVMs are feasible for use in system-on-panel (SOP) and 3-D stacked flash memory applications.

Comprehensive Study of N-Channel and P-Channel Twin Poly-Si FinFET Nonvolatile Memory

This paper develops the n-channel and p-channel twin poly-Si fin field-effect transistor nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results demonstrate that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.6 V after 104 program and erase cycles, and after 10 years, the charge is 53.4% of its initial value. In the future, it can be applied in multilayer Si ICs in fully functional system-on-panel, active-matrix liquid-crystal display and 3-D stacked flash memory.

Junctionless Poly-Si Nanowire FET With Gated Raised S/D

The short-channel effect (SCE) is an important issue in CMOS technology. In this paper, a junctionless (JL) poly-Si nanowire FET (NW-FET) with gated raised source/drain (S/D) was demonstrated to suppress the SCE. The gated raised S/D structure enhances the control of the channel by the gate. Therefore, a JL poly-Si NW-FET with the gated raised S/D exhibits reduced drain-induced barrier lowering and less channel length modulation effect. Additionally, when the gate bias exceeds the flat-band voltage, a JL poly-Si NW-FET with gated raised S/D exhibits a low parasitic S/D resistance owing to the formation of an accumulation layer in its S/D, which is useful for multi-gate-oxide applications. However, the gated raised S/D shows a high gate-induced drain leakage current in the off state. Therefore, the gate electrode of the gated raised S/D must be designed carefully to prevent high off current.

The physical analysis on electrical junction of junctionless FET

We propose the concept of the electrical junction in a junctionless (JL) field-effect-transistor (FET) to illustrate the transfer characteristics of the JL FET. In this work, nanowire (NW) junctionless poly-Si thin-film transistors are used to demonstrate this conception of the electrical junction. Though the dopant and the dosage of the source, of the drain, and of the channel are exactly the same in the JL FET, the transfer characteristics of the JL FET is similar to these of the conventional inversion-mode FET rather than these of a resistor, which is because of the electrical junction at the boundary of the gate and the drain in the JL FET. The electrical junction helps us to understand the JL FET, and also to explain the superior transfer characteristic of the JL FET with the gated raised S/D (Gout structure) which reveals low drain-induced-barrier-lowering (DIBL) and low breakdown voltage of ion impact ionization.