Yi-Ruei Jhan

Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length

We investigated the device performance of the optimized 3-nm gate length (LG) bulk silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The subthreshold slope values (SS ~ 65 mV/decade) and drain-induced barrier lowering (DIBL <; 17 mV/V) are analyzed in all three IM, AC, and JL modes bulk FinFET with |VTH| ~0.31 V. Furthermore, the threshold voltage (VTH) of the bulk FinFET can be easily tuned by varying the work function. This letter reveals that Moores law can continue up to 3-nm nodes.

Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

Performance Enhancement of Nanowire Tunnel Field-Effect Transistor With Asymmetry-Gate Based on Different Screening Length

This letter describes an asymmetric gate tunnel field-effect transistor (AG-TFET) with a gate-all-around (GAA) structure in the source and a planar structure in the drain. It has a low OFF-state current (6.55 ×10-16 A/μm) and a high ON-state current (2.47 ×10-5 A/μm) because the screening length λ of a GAA nanowire structure is half that of the planar structure. Simulations reveal that a subthreshold swing as low as 42 mV/decade and an ON/OFF current ratio as high as 1010 are realized. The AG-TFET is easily fabricated as an actual device by simply changing the layout of gate in a general TFET fabrication.

Performance Evaluation of Silicon and Germanium Ultrathin Body (1 nm) Junctionless Field-Effect Transistor With Ultrashort Gate Length (1 nm and 3 nm)

Silicon (Si) and Germanium (Ge) ultrathin body junctionless field-effect transistor (UTB-JLFET) with LG= 1 nm and LG = 3 nm were demonstrated by solving the coupled drift-diffusion and density-gradient model. The simulation results show that the Si and Ge channel can be used in ultrashort channel device as long as UTB is employed. As UTB is employed, ultra-short channel device does not need to follow an empirical rule of Teh = LG/3. Furthermore, Ge UTB-JLFET 6T-SRAM cell has reasonable static noise margin value of 149 mV. The circuit performances reveal that UTB-JLFET can be used for sub-5-nm CMOS technology nodes.

Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure

Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness (TCH) and gate length (LG). These devices (LG = 0.5 μm) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high ION/IOFF current ratio (106A/A) and practically negligible drain-induced barrier lowering (~0 mV/V). The ION current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications.

Pi-gate tunneling field-effect transistor charge trapping nonvolatile memory based on all tunneling transportation

This work demonstrates the feasibility of a charge-trapping nonvolatile memory based on Pi-gate polycrystalline silicon tunneling field-effect transistor, which has a silicon-oxide-nitride-oxide-silicon structure. Both the conducting current and the program/erase operations are based on quantum tunneling. In addition to a large threshold voltage shift of 4.7 V when Vg of 17 V is applied for only 1 ms, the proposed nonvolatile memory exhibits superior endurance of 88% after 104 P/E cycles. Moreover, only 35% of its initial charges are lost after ten years at a high temperature of 85 °C.

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory

This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor

Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length (λ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage (VBTBT) indicates clearly that TFET annealed by MWA had a lower λ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of 108, a low subthreshold swing, and an almost negligible drain-induced barrier lowering.

High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure

The novel trench junctionless poly-Si thin-film transistor (trench JL-TFT) with ultra-thin body (2.4 nm) is utilized to simple dry etching process. This novel devices show excellent performance in terms of steep SS (99 mV/dec.) and high I_ON/I_OFF (>10⁷). The I_ON current of the ultra-thin body (UTB) JL-TFT is increased by quantum confined effect.

Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory

This work presents p-channel and n-channel junctionless (JL) polycrystalline silicon (poly-Si) nanowires gate-all-around (GAA) nonvolatile memory (NVM) devices with silicon nanocrystals charge trapping layer. Experimental results indicate that the n-channel device has better programming efficiency and p-channel device has better erasing efficiency. For p-channel device, an extrapolation of the memory window to 10 yr demonstrates that 95% of the stored charge can be retained at high temperature of 85 °C. Such the p-channel and n-channel JL-GAA NVMs are feasible for use in system-on-panel (SOP) and 3-D stacked flash memory applications.