Muhammad Shaffatul Islam

Anomalous Staircase CV Characteristics of InGaSb-on-Insulator FET

Quasi-static capacitance voltage (CV) characteristics of In1-xGaxSb-on-insulator field-effect transistor (FET) are investigated using 1-D coupled Schrödinger-Poisson equations. Here, we report for the first time the staircase trend in the CV characteristics of such ultrathin-body FET. This observation is well correlated with the gate-bias-dependent electron concentration in different subbands. It is revealed that the staircase trend tends to disappear as the channel thickness increases above 15 nm. While the channel thickness and doping concentration-dependent shifts in CV curves are found to be significant, the composition-dependent shift is almost negligible.

On the Ballistic Performance of InGaSb XOI FET: Impact of Channel Thickness and Interface States

Here, we report the effect of channel thickness on the performance of a InGaSb-on-insulator FET with 15-nm gate length. The ballistic current-voltage characteristic is computed by nonequilibrium Greens function method using thickness-dependent effective mass, which is extracted from tight binding dispersion. Simulation result reveals that the threshold voltage and subthreshold slope decrease with decreasing channel thickness. Nearly three times enhancement in the ON-state current is observed for 3 nm compared with a 5-nm channel when the OFF-state current is made equal in each case by tuning the gate metal work function (WF). The drain-induced barrier lowering is found to decrease with decreasing channel thickness. However, interface states and roughness greatly affect the performance of such ultrathin-body device. Nevertheless, impact of interface states can be compensated by engineering the gate metal WF.

In x Ga 1– x Sb n-channel MOSFET: effect of interface states on CV characteristics

The capacitance-voltage (CV) characteristics of InGaSb based n-MOSFET are investigated by quantum mechanical calculation solving 1D self-consistent Schrodinger-Poisson equation using Silvacos ATLAS device simulation package. The charge density profile is determined with and without wave function penetration within the oxide layer and Neuman boundary condition. Quasi-static CV characteristics are studied both for the positive and negative interface charge densities. The results obtained from the simulation demonstrate that the significant shift in threshold voltage entirely depends on the polarity of the interface charge density. The oxide-dependent gate capacitance is also explained by simulating first eigen energy with and without wave function penetration.

Self-consistent quasi-static C-V characteristics of In 1−x Ga x Sb XOI FET

In1-xGaxSb XOI nFET is proposed and its capacitance-voltage (CV) characteristics are investigated. One dimensional coupled Schrödinger-Poisson equation is solved to calculate charge and hence to the capacitance. Well known SILVACOs ATLAS device simulation package is used to carry out the simulation. It is found that the CV characteristic as well as the threshold voltage of the proposed device depend on different process parameters like doping concentration, channel composition, channel thickness, gate oxide and oxide thickness, and operating temperature. Doping dependent threshold voltage shift is related with maximum allowable doping level, and which is also important for understanding enhancement mode operation.

Self-consistent quasi static CV characterization of In x Ga 1−x Sb buried channel n-MOSFET

The quasi-static capacitance-voltage (CV) characteristics of buried channel n-InGaSb MOSFET is investigated using SILVACOs ATLAS device simulation package. Self-consistent method is applied to solve the coupled one dimensional Schrödinger-Poisson equation taking into account of wave function penetration and strain effect. It is found that the CV profiles and threshold voltage are strongly depended on some important process parameters like oxide thickness, channel thickness, channel composition and temperature for buried channel InGaSb n-MOSFET.

Effect of gate length on the ballistic performance of nanoscale InGaSb double gate MOSFET

Effect of gate length on the ballistic performance of nanoscale In0.2Ga0.8Sb double gate n-MOSFET is studied. Non equilibrium greens function (NEGF) method is used to find the current-voltage characteristics. Well known SILVACOs ATLAS device simulation package is used to carry out the simulation. Three different gate length, 10nm, 13nm and 15 nm are analyzed. The simulation result shows that the drain current increases and the threshold voltage decreases with decrease in gate length. But the subthreshold swing increases with it. It reveals that the current voltage characteristic gets better but the electrostatic control of the gate becomes poorer with decrease in gate length.

Influence of band parameter of gate dielectrics on the ballistic performance at same EOT

Different high-k dielectrics have been supposed to provide same device performance if their physical thickness are not equal but equivalent, called “Equivalent oxide thickness” (EOT). For ultra thin body (UTB) devices like XOI, despite of EOT, conduction band offset (ΔE_C) at gate oxide-channel interface dominates the ballistic performance. In case of In_0.3Ga_0.7Sb XOI nFET using Al₂O₃ and HfO₂ with 0.5 nm EOT, we show the threshold voltage decreases and the subthreshold slope (SS) increases with increase in ΔE_C.

Ballistic performance comparison of InGaSb and InAsSb XOI nFET

Ballistic performance of nanoscale InGaSb and InAsSb XOI n-FET is compared using non equilibrium greens function (NEGF) method. The simulation results demonstrate that the ballistic performance is opposite to what is expected if the devices were long channel MOSFET. Although InAsSb possesses higher bulk electron mobility, but in ballistic regime, InGaSb gives higher drain current along with better subthreshold characteristic and reduced threshold voltage, if the off state current for both material is made equal.

Short channel InGaSb-on-insulator FET: With and without junctions

In this study the ballistic performance of III-V on insulator (XOI) and “junction less XOI” (JLXOI) nFET are investigated and compared by NEGF formalism, taking In0.3Ga0.7Sb as channel material. At 15nm gate length and 0.5nm EOT of gate dielectric the JLXOI shows significant improvement in threshold voltage (Vt) and ION with a fine tuned IOFF. Also the subthreshold slope (SS) reduced from 82.35mV/dec to 68.088mV/dec along with imporoved DIBL performance and simplified fabrication process.

Capacitance-Voltage characterization of InAs y Sb 1−y XOI FET

Self consistent quasi-static capacitance-voltage (CV) characteristics of InAsSb XOI nFET are investigated. Well known SILVACOs ATLAS device simulation package is used to solve one dimensional coupled Schrödinger-Poisson equation by correlating Fermi function and carrier concentration with growth co-ordinates. It is found that device operating temperature and different process parameters like doping concentration, channel composition, channel thickness, gate oxide and oxide thickness have strong influence on CV profiles and threshold voltage. It is also reported that there is a limit of doping concentration and channel thickness to ensure enhancement mode operation.