Munenori Tsuzuki

Scalable shared-buffering ATM switch with a versatile searchable queue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 /spl mu/m CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32/spl times/8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 /spl mu/m pure CMOS technology. By using four chip sets, a 622 Mbit/s 32/spl times/32 switch can be installed on one board.

622 Mb/s 8/spl times/8 shared multibuffer ATM switch with hierarchical queueing and multicast functions

A new ATM switch architecture, named the shared multibuffer architecture, features great advantages in the access speed, overall size of the buffer memories, and the cell loss performance. We have developed a 622 Mb/s 8/spl times/8 shared multibuffer ATM switch with multicast and hierarchical queueing functions to accommodate 156 Mb/s, 622 Mb/s and 2.4 Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to four sorts of 0.8-/spl mu/m BiCMOS LSIs and an ATM switch board. The switch board consists of four aligner-LSIs, nine buffer-LSIs and one control-LSI (or control/type 2-LSI). Possible applications to an ATM access system and a 2.4 Gb/s ATM loop system are also discussed.<<ETX>>

Evaluation of Mobile Ethernet switch on network processor

We have proposed Mobile Ethernet (Kuroda, M. et al., IEEE WCNC, 2004) to provide a mobility management mechanism on a widely deployed Ethernet network; it accommodates heterogeneous radio access systems, including 3G. Mobile Ethernet has features to realize fast handover across heterogeneous radio access systems using a mobility management mechanism at layer 2, and to achieve good scalability by partitioning the network in segments to suppress multicast messages. A network processor is a candidate hardware platform for the layer 2 switch which we call Mobile Ethernet switch. We discuss implementation of the switch using the Motorola network processor C-5e/spl trade/ while verifying its feasibility as a Mobile Ethernet switch. We evaluate the switch by the frame forwarding overhead and the number of MAC entries it can support compared to a typical layer 2 switch. We confirm that the Mobile Ethernet switch can forward MAC frames at the line speed of the Gigabit Ethernet by using parallel pipelines in aggregated channel processors in the network processor, though MAC address swapping for interface switching is added to a typical layer 2 switch. The overhead for the additional function is negligible because of the performance limitation of the physical interface in the case of Gigabit Ethernet. We also confirm that the switch can forward frames at gigabit speed by using a hash of more than 14 bits as lookup key for MAC address search, when there are up to 512k MAC entries. This performance and capacity are enough for our Mobile Ethernet assumptions.

A 622 Mb/s 32/spl times/32 scalable shared buffer ATM switch with searchable address queue

The advanced 0.5-/spl mu/m CMOS technology makes it possible to integrate a huge amount of memories and enables us to apply sophisticated architecture. The implementation of the ATM switch chipset, using new architectures named funnel-structured expandable architecture and the searchable address queueing scheme, is described. A 622 Mb/s 32/spl times/8 element switch consists of one buffer LSI and one control LSI. A 622 Mb/s 32/spl times/32 switch which comprises four element switches can be installed in one board. The switch has delay-priority control, cell-loss priority control, multicasting function and hierarchical queueing function to accommodate 156 Mb/s, 622 Mb/s and 2.4 Gb/s interfaces.