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Dive into the research topics where Harufusa Kondoh is active.

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Featured researches published by Harufusa Kondoh.


IEEE Journal of Solid-state Circuits | 2000

14-bit 2.2-MS/s sigma-delta ADC's

James C. Morizio; I.M. Hoke; T. Kocak; C. Geddie; C. Hughes; J. Perry; S. Madhavapeddi; M.H. Hood; G. Lynch; Harufusa Kondoh; T. Kumamoto; T. Okuda; H. Noda; M. Ishiwaki; T. Miki; Masao Nakaya

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 /spl mu/m CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADCs was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections.


symposium on vlsi circuits | 1990

A 10-bit 70 MS/s CMOS D/A converter

Yasuyuki Nakamura; Takahiro Miki; Atsushi Maeda; Harufusa Kondoh; Nobuharu Yazawa

A 10-bit 70-MS/s D/A (digital-to-analog) converter fabricated in a 1-mm CMOS process is described. A linearity within p0.5 LSB has been realized by a new switching sequence that is based on hierarchical error cancellation and suppresses both graded and symmetrical errors distributed in outputs of current sources. A layout technique for suppressing the influence of transistors implanted in tilt angles on linearity is also discussed


symposium on vlsi circuits | 1992

An 8*8 ATM switch LSI with shared multi-buffer architecture

Hiromi Notani; Harufusa Kondoh; Isamu Hayashi; Hideaki Yamanaka; Hirotaka Saito; Yoshio Matsuda; Masao Nakaya

An ATM switch LSI with a shared multibuffer architecture is proposed. With this architecture, a fourfold speed improvement is achieved in accessing buffer memories as compared to conventional shared-buffer-type switches, and high buffer memory utilization efficiency is also realized. This switch LSI is designed to operate at 100 MHz, using 0.8- mu m BiCMOS technology. Eight switch LSIs at 78-MHz operation construct a 622-Mb/s 8*8 ATM switching system with a buffer size of 8*128 ATM cells.<<ETX>>


symposium on vlsi circuits | 1990

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

Yutaka Arima; Koichiro Mashiko; Keisuke Okada; Tsuyoshi Yamada; Atsushi Maeda; Harufusa Kondoh; Shimpei Kayano

The authors propose a neural network chip that can organize the connection weight of each synapse with 125 neurons so that it can learn on chip. The chip employs the mixed design architecture of digital and analog circuits in a 1.0-mm CMOS technology. The chip operates more than 1000 times faster than conventional computers


european solid-state circuits conference | 1992

A 622Mbps 8×8 ATM Switch Chip Set with Shared Multi-Buffer Architecture

Harufusa Kondoh; Hiromi Notani; Hideaki Yamanaka; K. Higashitani; Hirotaka Saito; Isamu Hayashi; Shigeki Kohama; Yoshio Matsuda; Kazuyoshi Oshima; Masao Nakaya

An ATM (Asynchronous Transfer Mode) switch chip set utilizing the Shared Multi-Buffer architecture is described. While keeping the high buffer utilization efficiency, required access time for the buffer is greatly reduced compared with the conventional shared buffer type switches. This feature enables the high speed operation of the switch. Four Aligner-LSIs, bit sliced nine Buffer-Switch-LSIs and one Control-LSI construct a 622Mbps 8×8 ATM switch system operating at 78MHz. Using the time sharing method, 622Mbps and 155Mbps channels can be exchanged at a time.


international symposium on circuits and systems | 2000

SNDR sensitivity analysis for cascaded ΣΔ modulators

James C. Morizio; Mike Hoke; Taskin Kocak; Clark Geddie; Christopher C. W. Hughes; John Perry; Srinadh Madhavapeddi; Mike Hood; Ward Huffman; Takashi Okuda; Hiroshi Noda; Yasuo Morimoto; Toshio Kumamoto; Masahiko Ishiwaki; Harufusa Kondoh; Masao Nakaya; Takahiro Miki

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.


international symposium on circuits and systems | 2000

SNDR sensitivity analysis for cascaded /spl Sigma//spl Delta/ modulators

James C. Morizio; M. Hoke; Taskin Kocak; C. Geddie; Christopher C. W. Hughes; J. Perry; S. Madhavapeddi; M. Hood; W. Huffman; Takashi Okuda; Hiroshi Noda; Yasuo Morimoto; Toshio Kumamoto; Masahiko Ishiwaki; Harufusa Kondoh; Masao Nakaya; Takahiro Miki

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.


Archive | 1996

ATM local area network switch with dual queues

Hugh C. Lauer; Abhijit Ghosh; John H. Howard; Harufusa Kondoh; Randy B. Osborne; Chia Shen; Qin Zheng


IEICE Transactions on Electronics | 1995

A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector

Harufusa Kondoh; Hiromi Notani; Tsutomu Yoshimura; Hiroshi Shibata; Yoshio Matsuda


Archive | 1997

Signalformereinrichtung und Taktsignalzuführvorrichtung

Harufusa Kondoh; Masahiko Ishiwaki; Hiromi Notani

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Tsutomu Yoshimura

Osaka Institute of Technology

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