Hiromi Notani

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of a neural network by interconnecting multiple chips without reducing performance, is described. The chip integrates 336 neurons and 28224 synapses with a 1.0- mu m double-poly-Si double-metal CMOS technology. The operation speed is higher than 1*10/sup 12/ connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200-chip interconnections, the network will consist of 3360 neurons and 5,644,800 synapses. >

Scalable shared-buffering ATM switch with a versatile searchable queue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 /spl mu/m CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32/spl times/8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 /spl mu/m pure CMOS technology. By using four chip sets, a 622 Mbit/s 32/spl times/32 switch can be installed on one board.

A 622 Mb/s 32/spl times/8 scalable ATM switch chip set with on-chip searchable address queue

A 0.5 /spl mu/m CMOS 622Mb/s 32/spl times/8 shared-buffer ATM switch chip set consists ofa buffer LSI and a control LSI. It has a 768-cell on-chip buffer controlled by a searchable address queue running at 400 MHz with a double-edge triggered hand-shake circuit. The switch realizes 5 Gb/s total throughput with 8-level delay and 4-level cell-loss priorities for multimedia communications. A funnel structure enables a scalable switch size. 32 bit/frame synchronizers are integrated for all input channels.

A wide range 1.0 V-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors

We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15 /spl mu/m CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V.

A 0.9-/spl mu/A standby current DSP core using improved ABC-MT-CMOS with charge pump circuit

A 64-bit 80-MHz multimedia DSP core has been designed using 0.15-/spl mu/m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of the whole chip was simulated to optimize the size of the switch for the power supply control. The DSP core chip, which integrated 300 kgate logic, 64-kbyte SRAM and charge pump circuit, has only 0.9-/spl mu/A standby leakage current.