Hirotaka Saito

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8- mu m BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8*8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing. >

Scalable shared-buffering ATM switch with a versatile searchable queue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 /spl mu/m CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32/spl times/8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 /spl mu/m pure CMOS technology. By using four chip sets, a 622 Mbit/s 32/spl times/32 switch can be installed on one board.

An 8*8 ATM switch LSI with shared multi-buffer architecture

An ATM switch LSI with a shared multibuffer architecture is proposed. With this architecture, a fourfold speed improvement is achieved in accessing buffer memories as compared to conventional shared-buffer-type switches, and high buffer memory utilization efficiency is also realized. This switch LSI is designed to operate at 100 MHz, using 0.8- mu m BiCMOS technology. Eight switch LSIs at 78-MHz operation construct a 622-Mb/s 8*8 ATM switching system with a buffer size of 8*128 ATM cells.<<ETX>>

A 622Mbps 8×8 ATM Switch Chip Set with Shared Multi-Buffer Architecture

An ATM (Asynchronous Transfer Mode) switch chip set utilizing the Shared Multi-Buffer architecture is described. While keeping the high buffer utilization efficiency, required access time for the buffer is greatly reduced compared with the conventional shared buffer type switches. This feature enables the high speed operation of the switch. Four Aligner-LSIs, bit sliced nine Buffer-Switch-LSIs and one Control-LSI construct a 622Mbps 8×8 ATM switch system operating at 78MHz. Using the time sharing method, 622Mbps and 155Mbps channels can be exchanged at a time.