Mustafa Badaroglu

Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare

Abstract Internet of Things (IoT) offers a seamless platform to connect people and objects to one another for enriching and making our lives easier. This vision carries us from compute-based centralized schemes to a more distributed environment offering a vast amount of applications such as smart wearables, smart home, smart mobility, and smart cities. In this paper we discuss applicability of IoT in healthcare and medicine by presenting a holistic architecture of IoT eHealth ecosystem. Healthcare is becoming increasingly difficult to manage due to insufficient and less effective healthcare services to meet the increasing demands of rising aging population with chronic diseases. We propose that this requires a transition from the clinic-centric treatment to patient-centric healthcare where each agent such as hospital, patient, and services are seamlessly connected to each other. This patient-centric IoT eHealth ecosystem needs a multi-layer architecture: (1) device, (2) fog computing and (3) cloud to empower handling of complex data in terms of its variety, speed, and latency. This fog-driven IoT architecture is followed by various case examples of services and applications that are implemented on those layers. Those examples range from mobile health, assisted living, e-medicine, implants, early warning systems, to population monitoring in smart cities. We then finally address the challenges of IoT eHealth such as data management, scalability, regulations, interoperability, device–network–human interfaces, security, and privacy.

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D2) anneal, which is ascribed to a 2x reduction in interface trap density (DIT). Furthermore, it is found that (1) TMAH treatment of SiGe prior to HK deposition and (2) HK post-deposition annealing (PDA) are beneficial for DIT reduction as well, and that NBTI reliability is improved by both HP D2 anneal and TMAH treatment.

Impact of Wire Geometry on Interconnect RC and Circuit Delay

We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low-k damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low-k sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, R and C pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay.

Internet-of-Things and big data for smarter healthcare: from device to architecture, applications and analytics

Abstract The technology and healthcare industries have been deeply intertwined for quite some time. New opportunities, however, are now arising as a result of fast-paced expansion in the areas of the Internet of Things (IoT) and Big Data. In addition, as people across the globe have begun to adopt wearable biosensors, new applications for individualized eHealth and mHealth technologies have emerged. The upsides of these technologies are clear: they are highly available, easily accessible, and simple to personalize; additionally they make it easy for providers to deliver individualized content cost-effectively, at scale. At the same time, a number of hurdles currently stand in the way of truly reliable, adaptive, safe and efficient personal healthcare devices. Major technological milestones will need to be reached in order to address and overcome those hurdles; and that will require closer collaboration between hardware and software developers and medical personnel such as physicians, nurses, and healthcare workers. The purpose of this special issue is to analyze the top concerns in IoT technologies that pertain to smart sensors for health care applications; particularly applications targeted at individualized tele-health interventions with the goal of enabling healthier ways of life. These applications include wearable and body sensors, advanced pervasive healthcare systems, and the Big Data analytics required to inform these devices.

Sustaining Moore’s Law with 3D Chips

Rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore’s law on its traditional scaling path.

Holistic technology optimization and key enablers for 7nm mobile SoC

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (R_wire) multiplied by logic gate input pin cap (C_pin), R_wire×C_pin, is identified as a major limiter of performance and power at N7. Reducing C_pin is crucial to mitigate abruptly rising BEOL R_wire effect. Depopulation of fin is one of most effective methods to reduce C_pin, and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce C_pin, whose benefit is enhanced by reduction of other C_pin components. Careful choice of routing metal stack ameliorates adverse effect of R_wire. Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (P_fin) is needed to reduce transistor resistance (R_tr). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.

Modeling of Via Resistance for Advanced Technology Nodes

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step.

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes

We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to authors previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.

Interconnect-aware device targeting from PPA perspective

CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, power, and area with thanks to Moores law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. It is empirical to consider the system-on-chip (SoC) context to choose the most critical process knobs since most of processing budget to scale a technology node is already consumed by increasing process steps due to multiple patterning. In this paper we will show that the device parasitics and the interconnect resistance are the most critical performance scaling barriers for technology nodes beyond 7 nm (N7). We will demonstrate the impact of process and design knobs enabling performance and power improvements for the N7 node as defined in ITRS 2015 edition while still continuing to scale the area to limit the cost.

More Moore landscape for system readiness - ITRS2.0 requirements

CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moores law. System scaling is getting more difficult with the limitations in interconnect and bandwidth per power as well as the difficulties and cost of monolithic integration. This requires a holistic approach for an optimal balance of performance and power under the limits of technology. This paper covers a portfolio of More Moore technologies for power-aware device enabling value proposition for system scaling - where requirements and gaps will be addressed in the ITRS2.0 roadmap.