Mustafa Kilic

Column-separated compressive sampling scheme for low power CMOS image sensors

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement matrix generation in a single clock cycle. As a result, high frame rates and low power consumption are achievable with an acceptable reduction in raw image quality for many practical video applications. Physical IC design issues such as device mismatch, noise and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. As a proof-of-concept, specialized pixels, Comparator-Based Switched Capacitor readout and Column-Parallel Differential Cyclic-ADCs are designed in a 0.18μm standard CMOS technology. The simulation results of the proposed circuit show that a 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed scheme can easily be applicable in different circuit design solutions and scaled towards newer technology nodes and higher image resolutions.

Power-efficient CMOS image acquisition system based on compressive sampling

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Column-Parallel Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are discussed. The final simulation results show that the proposed 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The architecture can easily be scaled towards newer technology nodes and higher image resolutions.

A DAC assisted speed enhancement technique for high resolution SAR ADC

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MSB capacitors get thus longer, limiting the total conversion speed. This method proposes to operate a small and fast 3-bit ADC in parallel with the main one to determine rapidly the MSB values, while the capacitors of the main DAC have not settled yet. An error correction circuit detects and corrects automatically any decision error due to mismatch between the two DACs. A design example of a 10-bit ADC is implemented in 28nm FDSOI CMOS technology to illustrate this technique. A sampling rate of 800MS/s is achieved without any effort for reducing the capacitive DAC size.

A hybrid CDAC - threshold configuring SAR ADC in 28nm FDSOI CMOS

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds for the remaining 4 LSBs. The DAC capacitance at the front-end remains small enough to achieve high sampling rate with increased input bandwidth. Two asynchronously clocked alternate comparators are used additionally to improve conversion speed. The ADC is designed and simulated in 28nm FD-SOI CMOS. It consumes 4.1 mW from a 1V supply, while achieving a SNDR of 52.1 dB and a Figure-of-Merit of 11.4 fJ/conversion-step.

An implantable high-voltage cortical stimulator for post-stroke rehabilitation enhancement with high-current driving capacity

This paper presents a high-voltage, high-current implantable cortical stimulation integrated circuit aiming at supporting the rehabilitation of patients suffering from stroke. In this context, a large area of the motor cortex needs to be stimulated, requiring high current densities at the electrode-electrolyte interface. The designed integrated circuit contains eight fully programmable stimulation channels generating biphasic constant current pulses up to 8mA from a 20V supply. The current mismatch between positive and negative pulses has been evaluated at 0.03%. The chip has been fabricated in an AMS 0.18μm high-voltage CMOS process, and has a die area of 5mm2.

High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]

A novel compressive sampling scheme suitable for highly scalable hardware implementation is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to achieve high frame rates and maintain low power consumption. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Per-column Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the required dynamic range, device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. The final simulation results show that the proposed 256x256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed architecture can easily be scaled towards newer technology nodes and higher image resolutions.