Nikola Katic

Sensorless position detection of a linear actuator using the resonance frequency

This paper presents a method to detect the position of a linear actuator without any position sensor. The actuator winding has a resonance frequency that is very related to the position of the linear actuator moving part. A sinusoidal scan voltage is superposed to the main voltage. Its frequency is close to the resonance frequency and therefore it is possible to measure the resulting scan current amplitude that allows position detection.

Column-separated compressive sampling scheme for low power CMOS image sensors

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement matrix generation in a single clock cycle. As a result, high frame rates and low power consumption are achievable with an acceptable reduction in raw image quality for many practical video applications. Physical IC design issues such as device mismatch, noise and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. As a proof-of-concept, specialized pixels, Comparator-Based Switched Capacitor readout and Column-Parallel Differential Cyclic-ADCs are designed in a 0.18μm standard CMOS technology. The simulation results of the proposed circuit show that a 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed scheme can easily be applicable in different circuit design solutions and scaled towards newer technology nodes and higher image resolutions.

Compressive image acquisition in modern CMOS IC design

Compressive sampling CS offers bandwidth, power, and memory size reduction compared to conventional Nyquist sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor CMOS image sensors, cameras, and camera systems. However, very few integrated circuit IC designs based on CS exist because of the missing link between the well-established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non-idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs. Copyright

Power-efficient CMOS image acquisition system based on compressive sampling

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Column-Parallel Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are discussed. The final simulation results show that the proposed 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The architecture can easily be scaled towards newer technology nodes and higher image resolutions.

A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces

A continuous-time (CT) ΣΔ modulator for sensing and direct analog-to-digital conversion of nA-range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source-coupled logic cells to efficiently convert subthreshold current to digital code without performing current-to-voltage conversion. As a benefit of this technique, the current-sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low-power and low-voltage current-mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal-oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current-sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current-mode analog-to-digital converter designs and is comparable with the voltage-mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current-mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current-mode output in ultra low-power conditions and is also suitable to perform on-chip current measurements in power management circuits.

A Relative Imaging CMOS Image Sensor for High Dynamic Range and High Frame-Rate Machine Vision Imaging Applications

This paper proposes an unconventional image acquisition scheme for machine vision applications, based on detecting ratios of illumination (pixel) intensities. Detecting relative ratios enables capturing the scene features and patterns almost independently from the local scene illumination resulting in potentially extremely high dynamic range. Moreover, detecting signal ratios using a fully differential circuit optimally suits the intrinsic nature of very large scale integrated design. A scalable and compact hardware implementation is proposed as a proof-of-concept toward relative image acquisition. The proposed photo-current-ratio-detecting pixels completely bypass the need of conventional photo-current integration which enables high frame-rate operation of up to 24000 frames/s. The pulse-width modulated output of the proposed pixel is captured by compact column-parallel readout circuits based on digital counters. The developed 32 × 32 pixel array prototype CMOS image sensor consumes 4 mW of power operating at a nominal 9765 frames/s frame rate, and 6.8 mW of power operating at a maximum 24000 frames/s. The presented prototype design is fully scalable toward newer CMOS fabrication nodes and higher sensor resolution.

A retina-inspired robust on-focal-plane multi-band edge-detection scheme for CMOS image sensors

An edge-detection scheme suitable for machine vision and digital motion detection applications is presented. The scheme is inspired by the human visual system (human retina) and modified for a compact and scalable CMOS hardware implementation. In addition, pixel circuit and implementation of the scheme on a CMOS focal-plane are proposed and simulation results are presented. The circuit performs thresholding and single-bit quantization of high-frequency image content over multiple frequency bands using a low-complexity down-sampling scheme. As a result, a 1-bit per pixel output is obtained which results in efficient edge-detection of the image content. Depending on the number of the utilized frequency bands, the presented scheme achieves image compression levels that range from 1 BPP (bit-per-pixel) to 1.33 BPP. The proposed acquisition technique and the corresponding CMOS circuit can easily be adjusted to various imaging applications and scaled towards new CMOS technology nodes and high resolution image sensors.

CMOS-integrated photodetectors for neuromorphic and smart imaging applications: A low-cost design and measurement method

Several on-chip photodetecting device structures are designed using a low-cost standard 0.18μm CMOS process. The comparison in terms of measured light responsivity and the response speed is presented between conventional and comb-shaped Nwell-Psubstrate photodiodes, conventional and comb-shaped, vertical and lateral bipolar-junction phototransistors and a Darlington pair of bipolar-junction phototransistors. The photodetectors are embedded in a conventional three transistor active pixel topology and measured using a customized low-cost measurement setup. The presented comparative study targets neuromorphic and smart imaging applications where the pixel light responsivity and the response speed are crucial performance merits. The study demonstrates the benefits of using standard-CMOS-compatible bipolar-junction structures in these applications. Therefore, the pixel responsivity and response speed are measured for each structure and the results are presented in detail.

A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder

The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion (TDC) technique is introduced which performs the complete conversion within a single clock cycle. The measurement results show that the proposed 5-bit converter achieves an 80MHz sampling rate while consuming 900µW of power from the 1.8V supply voltage. The prototype ADC is developed in a 180nm standard CMOS technology and achieves the power efficiency of 445fJ/conversion which is comparable to many existing state-of-the-art flash ADCs. The measured performance is achieved without any design optimization or circuit calibration techniques confirming the promising benefits of the proposed topology. Thanks to the fully-digital structure, the circuit enables a robust and compact implementation which is very convenient for interleaving and beneficial for many potential applications.

A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process

A variety of smart imaging and neuromorphic applications perform time-domain image acquisition in order to imitate biological systems and reduce the growing transmission bandwidth of the modern imaging devices. Because they operate in time-domain, they require the highest possible pixel responsivity and response speed. This work provides a comparative experimental study of different unconventional photodetecting structures with respect to these parameters. Several on-chip photodetecting device structures are designed using a low-cost standard 0.18 µ m CMOS process. The comparison in terms of measured quantum efficiency, light responsivity and the response speed is presented between conventional and comb-shaped N-well/P-substrate photodiodes, conventional and comb-shaped, vertical and lateral photo-bipolar-junction-transistors (photo-BJTs) and a Darlington pair of bipolar-junction phototransistors. The photodetectors are embedded in a conventional three transistor active pixel topology and measured using a customized low-cost measurement setup. The pixel quantum efficiency, responsivity and response speed are measured for each structure and the results are presented in detail. The obtained results demonstrate the benefits of using standard-CMOS-compatible BJT structures in time-domain applications. The BJT-based photodetectors show increased responsivity to green-yellow light region (500-600nm wavelength) compared to conventional N-well/P-substrate diode. The highest responsivity is achieved by a combination of lateral and vertical BJT. The fastest response is achieved by the rarely used Darlington pair configuration of BJTs, which demonstrates the potential benefit of using this structure for time-domain imaging applications. A low-cost measurement setup and the measurement methodology are described in detail to make the experiment reproducible for any other standard CMOS process.