Mahdad Hosseini Kamal

Compact Low-Power Cortical Recording Architecture for Compressive Multichannel Data Acquisition

This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 \mbi μm CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 \mbi μW of power within an effective area of 250 \mbi μm × 250 \mbi μm per channel.

Compressive multichannel cortical signal recording

This paper presents a novel approach to acquire multichannel wireless intracranial neural data based on a compressive sensing scheme. The designed circuits are extremely compact and low-power which confirms the relevance of the proposed approach for multichannel high-density neural interfaces. The proposed compression model enables the acquisition system to record from a large number of channels by reducing the transmission power per channel. Our main contributions are the twofold. First, a CMOS compressive sensing system to realize multichannel intracranial neural recording is described. Second, we explain a joint sparse decoding algorithm to recover the multichannel neural data. The idea has been implemented at system as well as circuit levels. The simulation results reveal that the multichannel intracranial neural data can be acquired by compression ratios as high as four.

Column-separated compressive sampling scheme for low power CMOS image sensors

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The scheme utilizes an identical pseudo-random sequence for every image column, therefore reducing in-pixel hardware complexity and allowing measurement matrix generation in a single clock cycle. As a result, high frame rates and low power consumption are achievable with an acceptable reduction in raw image quality for many practical video applications. Physical IC design issues such as device mismatch, noise and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. As a proof-of-concept, specialized pixels, Comparator-Based Switched Capacitor readout and Column-Parallel Differential Cyclic-ADCs are designed in a 0.18μm standard CMOS technology. The simulation results of the proposed circuit show that a 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed scheme can easily be applicable in different circuit design solutions and scaled towards newer technology nodes and higher image resolutions.

Tensor low-rank and sparse light field photography

We present a computational camera system for efficient light field image and video acquisition.Our mathematical framework models the intrinsic low dimensionality of light fields using tensor low-rank and sparse priors.We design and implement a prototype compressive light field camera that avoids capturing redundancy of high-dimensional plenoptic function. High-quality light field photography has been one of the most difficult challenges in computational photography. Conventional methods either sacrifice resolution, use multiple devices, or require multiple images to be captured. Combining coded image acquisition and compressive reconstruction is one of the most promising directions to overcome limitations of conventional light field cameras. We present a new approach to compressive light field photography that exploits a joint tensor low-rank and sparse prior (LRSP) on natural light fields. As opposed to recently proposed light field dictionaries, our method does not require a computationally expensive learning stage but rather models the redundancies of high dimensional visual signals using a tensor low-rank prior. This is not only computationally more efficient but also more flexible in that the proposed techniques are easily applicable to a wide range of different imaging systems, camera parameters, and also scene types.

Compressive image acquisition in modern CMOS IC design

Compressive sampling CS offers bandwidth, power, and memory size reduction compared to conventional Nyquist sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor CMOS image sensors, cameras, and camera systems. However, very few integrated circuit IC designs based on CS exist because of the missing link between the well-established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non-idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs. Copyright

Power-efficient CMOS image acquisition system based on compressive sampling

A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Column-Parallel Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are discussed. The final simulation results show that the proposed 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The architecture can easily be scaled towards newer technology nodes and higher image resolutions.

A Convex Solution to Disparity Estimation from Light Fields via the Primal-Dual Method

We present a novel approach to the reconstruction of depth from light field data. Our method uses dictionary representations and group sparsity constraints to derive a convex formulation. Although our solution results in an increase of the problem dimensionality, we keep numerical complexity at bay by restricting the space of solutions and by exploiting an efficient Primal-Dual formulation. Comparisons with state of the art techniques, on both synthetic and real data, show promising performances.

Joint low-rank and sparse light field modelling for dense multiview data compression

The effective representation of the structures in the multiview images is an important problem that arises in visual sensor networks. This paper presents a novel recovery scheme from compressive samples which exploit local and non-local correlated structures in dense multiview images. The recovery model casts into convex minimization framework which penalizes the sparse and low-rank constraints on the data. The sparsity constraint models the correlations among pixels in a single image whereas the global correlations across images are modelled with the low-rank prior. Simulation results demonstrate that our approach achieves better reconstruct quality in comparison with the state-of-the-art reconstruction schemes.

High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]

A novel compressive sampling scheme suitable for highly scalable hardware implementation is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to achieve high frame rates and maintain low power consumption. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Per-column Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the required dynamic range, device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are presented and discussed. The final simulation results show that the proposed 256x256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The proposed architecture can easily be scaled towards newer technology nodes and higher image resolutions.

Interconnected Network of Cameras

The real-time development of multi-camera systems is a great challenge. Synchronization and large data rates of the cameras adds to the complexity of these systems as well. The complexity of such system also increases as the number of their incorporating cameras increases. The customary approach to implementation of such system is a central type, where all the raw stream from the camera are first stored then processed for their target application. An alternative approach is to embed smart cameras to these systems instead of ordinary cameras with limited or no processing capability. Smart cameras with intra and inter camera processing capability and programmability at the software and hardware level will offer the right platform for distributed and parallel processing for multi- camera systems real-time application development. Inter camera processing requires the interconnection of smart cameras in a network arrangement. A novel hardware emulating platform is introduced for demonstrating the concept of the interconnected network of cameras. A methodology is demonstrated for the interconnection network of camera construction and analysis. A sample application is developed and demonstrated.