Myung-Hee Na

The effective drive current in CMOS inverters

A simple but accurate expression for the effective drive current, I/sub eff/, for CMOS inverter delay is obtained. We show that the choice I/sub eff/=(I/sub H/+I/sub L/)/2, where I/sub L/=I/sub ds/(V/sub gs/=V/sub dd//2,V/sub ds/=V/sub dd/), and I/sub H/=I/sub ds/(V/sub gs/=V/sub dd/,V/sub ds/=V/sub dd//2) is defined, accurately predicts inverter delay when tested against compact models over a variety of conditions and against hardware results in 90 nm node technology. Furthermore, this definition of I/sub eff/ accurately captures the delay behavior of non-traditionally scaled devices, where mobility and V/sub T//V/sub dd/ are scaled in neither a regular nor uniform manner.

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (TINV) , threshold voltage (VTH), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor VTH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant VTH variability in the present HKMG technology.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinvs down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

A comparative DC and AC performance evaluation between tri-gate FinFETs and gate-all-around nanowire FETs is carried out for potential sub-7nm technology node. The comparative analysis of the intrinsic and parasitic components using the classical drift-diffusion transport and quantization models indicates that a wider and thinner stacked nanosheet-type design can address the issues associated with conventional nanowire devices while demonstrating improved performance relative to FinFET. The optimization of the wire suspension region is found to be critical for Ieff-Ceff performance trade-offs.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay

This paper reports the SOI 90 nm statistical model to hardware correlation achieved over a broad voltage, temperature and a variety of five different ring oscillators. Monte Carlo simulations were performed and compared with the measured circuit statistical population. A sub-ps model to hardware correlation accuracy was achieved between the mean hardware and simulated delays. Based on the model validation, a parasitic aware layout optimization was performed on a constrained and an unconstrained inverter leading to a 5 and 66 % reduction in delay of the inverter reference circuit. The unconstrained parasitic aware optimization achieves a record inverter switching delay of 1.94 ps

On the difference of temperature dependence of metal gate and poly gate SOI MOSFET threshold voltages

The temperature dependence of device performance is a critical factor that determines overall product power-performance. We show HKMG gate stacks drive significantly higher threshold temperature dependence over poly-Si/SiON. We further show that in SOI, the work-function engineering enabled by HKMG integration schemes can result in even higher Vt temperature sensitivity attributed to differences in floating body behavior. These combined effects, together with observed reduced mobility temperature sensitivity, result in higher drive current at elevated temperature. This is in contrast to poly-Si/SiON technologies where the low driven current, performance limiting corner is typically at high temperature.

Revisiting the impact on sub-threshold regions in uniaxially-strained FETs

Abstract withdrawn