Myung-Woon Hwang

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements

A high IIP2 direct-conversion mixer using an even-harmonic reduction technique for cellular CDMA/PCS/GPS applications

An even-harmonic reduction technique to enhance IIP2 (second order input intercept point) performance in a direct-conversion mixer is proposed based on a simplified analysis of second-order intermodulation. Using the proposed technique, IIP2 performance can be improved while reducing sensitivity to operating condition and output load mismatch. Direct-conversion mixers for cellular CDMA, PCS, and GPS applications are designed and fabricated in a 0.35 /spl mu/m SiGe BiCMOS process. Measurement results show 40 dB improvement and reduced sensitivity of IIP2, which are consistent with simulation results.

A High IIP2 Direct-Conversion Receiver Using Even-Harmonic Reduction Technique for Cellular CDMA/PCS/GPS Applications

A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 mum SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a DC calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA; 68 dBm IIP2, - 3.7 dBm IIP3, and 2.9 dB NF for PCS; and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS.

A fully-integrated low power direct conversion transmitter with fractional-N PLL using a fast AFC technique for CDMA applications

The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to implement automatic frequency calibration (AFC). Total locking time is approximately 200 /spl mu/s, including 80 /spl mu/s AFC lock time. Total current consumption for -80 dBm, -10 dBm, and 8 dBm output power are 27 mA, 33 mA, and 60 mA, respectively. This chip is housed in a small 5 mm /spl times/ 5 mm 32 pin MLF package.

A 1.2V 57mW mobile ISDB-T SoC in 90nm CMOS

This paper presents a 1.2 V 57 mW SoC using a 90 nm CMOS process in mobile ISDB-T application. This achieves −98.5 dBm sensitivity at QPSK, CR = −2/3 with 2.5 dB NF of RF tuner block and 5.6 dB C/N of OFDM block at UHF-band. To integrate RF tuner and OFDM in a small single die, a wideband single LC-VCO operating from 1.8 GHz to 3.3 GHz is proposed and OFDM is designed by hard-wired logic.

Design of high speed CMOS prescaler

A high-speed divide-by-2 prescaler is designed in a 0.8 um CMOS. New ECL-like D flip-flop is proposed having source-folded diode clamping. Significant amount of speed up can be obtained using source-folded diode with proper sizing ratio of transistors, and lower power consumption can be obtained by designing low power D flip-flop and removing additional input-amplifying buffer. The simulated maximum input frequency of the suggested prescaler reaches up to 3.15 GHz with only 5 mA and 1.8 GHz with 1.6 mA at 3.3 V.

A Fully Integrated Low-IF Image Reject Receiver for T-DMB and DAB Applications

This paper describes a fully integrated low-IF image reject receiver for triple-band T-DMB and DAB applications. The receiver features an efficient local oscillator (LO) frequency planning using a wideband low phase noise voltage-controlled oscillator (VCO) for improved low-IF receiver performance. The tuning range of the VCO is measured from 2.65 to 3.95GHz covering all the required frequency bands (Band-II, Band-Ill, and L-Band). The receiver shows a measured noise figure (NF) of under 2dB, thereby achieving a sensitivity of lower than -100dBm with 100mW power consumption. The maximum input signal level of the receiver is lOdBm, resulting in HOdB dynamic range. Total image rejection of over 50dB is achieved. The receiver is fabricated in a 0.25-mum BiCMOS process and packaged in a 5mm x 5mm 32-pin MLF package.

A precise temperature-insensitive and linear-in-dB variable gain amplifier

A fully temperature-compensated linear-in-dB variable gain amplifier (VGA) is presented. The VGA achieves wide dynamic range and precise linear-in-dB control capability using a translinear current amplifier. The compensation technique having current proportional to the squared temperature is proposed. The VGA is implemented with 0.35 /spl mu/m SiGe BiCMOS process. Greater than 90 dB dynamic range while having only /spl plusmn/3 dB gain drift from -30/spl deg/C to 85/spl deg/C temperature range is measured.

Session 20 overview: Wireless systems: Wireless subcommittee

State-of-the-art wireless systems implemented in low-cost, deep-sub-micron CMOS processes support a wide range of applications including mm-Wave ranging, Gb/s communications in 60GHz/5GHz bands and cost-sensitive cellular communications. This session includes one radar receiver paper, three state-of-the-art 60GHz transceivers supporting 2 to 28Gb/s, the first reported fully integrated 802.11a/b/g/n/ac SoC supporting over 1Gb/s and three cellular receivers implementing blocker-tolerant techniques intended to eliminate the need for external filters.

Session 21 overview / wireless: Cellular

Summary form only given. In most parts of the world the cellular mobile terminal market is starting to move from 2G and 3G to 4G systems in order to support higher date rates in the popular smart phones, netbooks and other mobile devices. These higher data rates are enabled by 3G standards such as WCDMA/HSPA and by 4G standards such as LTE. Another evolving direction is the removal of external components, aiming at lower-cost mobile devices and a higher integration level of functions, including a large number of bands and multistandard operation to guarantee global coverage.