N. A. F. Othman

Performance and Device Design Based on Geometry and Process Considerations for 14/16-nm Strained FinFETs

The multigated architecture of FinFETs appear attractive for continued CMOS scaling with the addition of discrete fin sizing that brings a new variable into the design. In this paper, a comprehensive 3-D simulation on 14/16-nm advanced-process FinFET under geometric and process considerations was presented in order to achieve the best possible performance with minimal penalty. Geometric designs, specifically the width and height of the fins as well as the channel lengths, were imposed onto the FinFET, and the impact on the performance merits and devices characteristics was analyzed. The influence of stress engineering, metal gate work function (WF), and doping concentration was further explored for an allowable leakage limit. The simulation suggests that the process-induced stress can boost the 14/16-nm FinFET drain current up to two or three times. It was also found that the channel length is the most critical geometric parameter to affect the performance of both the pFinFET and nFinFET, of which 60% and 50% increases in its respective drain current were observed as the channel length is scaled from 35 nm to 15 nm. In addition, a change in metal WF is found to be the most effective method for the adjustment of threshold voltage.

Performance of 7nm stress-engineered nFinFETs based on stressors consideration for different channel material

Selecting the material used as the device channel which connects the source to drain region is vital as it will affect the conductivity of the transistor. Recently, germanium was actively used as the diffusion material for source/drain and channel properties mainly for ρ type FinFET, however rarely in η type FinFET. This paper investigates the device performance of 7nm nFinFET for their various types of stressor: channel and source/drain stressor by employing germanium as diffusion materials which indicates the strain applied to the device investigated. It was observed that with the incorporation of germanium inside silicon channel (depending on the ratio of Si1-xGex) and reducing the diffused germanium inside source/drain region, the Id-Vg characteristics seems to be better and shows enhanced performance. It was also observed that the drain current for nFinFET in linear mode can be increased up to 60% with the incorporation of germanium and by increasing the mole fraction of germanium inside source/drain region, the drain current can reduce up to 40% and 30% for silicon and silicon germanium channel respectively. In addition, with only 15%-30% of germanium present inside the source/drain region, the device seems to have a better performance with higher drain current.

The application of Taguchi method on the robust optimization of p-FinFET device parameters

Determining the exact device parameter for a particular transistor is crucial in order to ensure the device is operating at their best possible conditions. This paper discusses the application of Taguchi method on device parameter design for a 7nm germanium p-FinFET with optimization using design of experiments. In this work, the Sentaurus Simulator is used as the medium of simulation and analysis. The Taguchi method was implemented to determine the most appropriate combination of factors for robust device performance using orthogonal arrays, signal-to-noise ratio as well as Pareto analysis of variance as the quality characteristic of choices. The factors involved in the design of experiments include the length and height of the fin as well as the width of the fin at the top region. The on-state current and off-state current were considered using these methods by applying larger the better and smaller the better characteristics respectively. Using Taguchis robust performance signal-to-noise ratio and Pareto analysis of variance, the combination of parameters with high on-current and low off-current were obtained. It is observed that with fin length of 8nm, height of 35nm and width of 7nm, the best performance in terms of on-current for p-FinFET can be achieved with the values of 1.8847mA. On the contrary, with dimensions fin length of 15nm, height of 25nm and width of 2nm can leads to best performance in terms of off-current with the values of 26.7nA.

Impact of Channel, Stress-Relaxed Buffer, and S/D Si 1− x Ge x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Stress-engineered fin-shaped field effect transistors (FinFET) using germanium (Ge) is a promising performance booster to replace silicon (Si) due to its high holes mobility. This paper presents a three-dimensional simulation by the Sentaurus technology computer-aided design to study the effects of stressors—channel stress, stress-relaxed buffer (SRB), and source/drain (S/D) epitaxial stress—on different bases of FinFET, specifically silicon germanium (SiGe) and Ge-based, whereby the latter is achieved by manipulating the Ge mole fraction inside the three layers; their effects on the devices’ figures-of-merits were recorded. The simulation generates an advanced calibration process, by which the drift diffusion simulation was adopted for ballistic transport effects. The results show that current enhancement in p-type FinFET (p-FinFET) with 110% is almost twice that in n-type FinFET (n-FinFET) with 57%, with increasing strain inside the channel suggesting that the use of strain is more effective for holes. In SiGe-based n-FinFET, the use of a high-strained SRB layer can improve the drive current up to 112%, while the high-strain S/D epitaxial for Ge-based p-FinFET can enhance the on-state current to 262%. Further investigations show that the channel and S/D doping are affecting the performances of SiGe-based FinFET with similar importance. It is observed that doping concentrations play an important role in threshold voltage adjustment as well as in drive current and subthreshold leakage improvements.

Effect of gate recess variation on electrical characteristics and 2DEG transport of InGaAs high electron mobility transistors

In this paper, analysis of the gate recess variation on DC and RF characteristics on 0.25um psuedomorphic high electron mobility transistor using Sentaurus TCAD simulation have been carried out. Hydrodynamic transport model have been employed for the simulation. Furthermore, off state breakdown characteristics are also exploited, while exploring the essential features of 2-dimensional electron gas (2DEG) through self-consistent solution of Schrodinger and Poissons equation. Results signifies wide gate recess structure are capable of having high cutoff frequency (FT) and maximum frequency of oscillation (Fmax) up to 73.69 Ghz and 228.69 Ghz respectively but drain saturation current aggregates at the same time, simultaneously deteriorating electron density and mobility. Narrow gate recess devices have better current handling capabilities with superior DC output and transfer characteristics with prominent improvement in density of electrons but switching frequencies and breakdown voltage are detrimental, suppressing its safe operation at elevated temperature. Therefore an optimized gate recess length have been proposed while maintaining small gate to channel distance to minimize short channel effect; it allows a satisfactory tradeoff between current driving capability, frequency response and remarkable sheet carrier density besides having reasonable breakdown voltage. The proposed gate recess HEMT structure shows excellent qualifications as emerging candidate for high speed, low power logic applications.

Impacts of fin width scaling on the electrical characteristics of 10-nm FinFET at different metal gate work function

This paper investigates the effects of top fin width scaling (Wtop = 4, 6, 8 nm) of p-and n-type 10-nm FinFET on the electrical performance of the device, specifically optimized for low performance (LP) and high performance (Hp) devices. The work also studies the correlation of the metal work function to the device performance. It is observed that the transfer characteristics shown increased drain current in linear region towards increased Wtop for both p- and n-FinFET. The threshold voltage is shifted to the right for p-FinFET as the work function is increased. Oppositely for n-FinFET, they shifted to the left as the work function reduced. The Ion/Ioff ratio reduced as width increase. The observations on Ion/Ioff ratio for low performance device show the magnitude drops to 63% and 82% in n-FinFET and p-FinFET, respectively when the fin width is changed from 4 nm to 8 nm.