S. F. Wan Muhamad Hatta

NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations

Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advancedprocess high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased.

Effects of the fin width variation on the performance of 16 nm FinFETs with round fin corners and tapered fin shape

The rapid scaling of the CMOS technology is causing the evaluation from conventional planar MOSFETs to the FinFET architecture, particularly in the 22 nm and 14 nm technology nodes. FinFETs technologies ensure low power usage and better area utilization, as well as traditional scaling improvements. It was observed that for FinFETs, the smaller the width of the fin, the better the characteristics. It was observed that drain current characteristics of the NFinFET and PFinFET at both the linear and saturation regime would decrease in magnitude as the width of the fin was decreased. The Ion/Ioff ratio generally decreases as the width of the fin increases. The NFinFET particularly exhibits a significant drop in the Ion/Ioff of to nearly 50% for a change of fin width from 5nm to 15nm.

Effects of gate stack structural and process defectivity on high- k dielectric dependence of nbti reliability in 32 nm technology node PMOSFETs

We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2) and hafnium oxide (HfO2) layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

Characterization of NBTI-induced positive charges in 16 nm FinFET

Negative Bias Temperature Instability (NBTI) is one of the most critical reliability problems in nano-scale p-MOSFETs. The NBTI-induced positive charges cause threshold voltage shifts, hence degrading the performance of the device. However, the characteristics of the positive charges (PC) in FinFET devices are currently not well-understood. In this work, a numerical simulation using an energy profiling technique on a 3D FinFET structure suggests that the positive charges are sensitive to energy level and differ considerably over the energy range, in agreement with the published measurements. The PCs which are distributed below, within and above the energy bandgap are known as as-grown hole traps (AHT), cyclic positive charges (CPC) and antineutralization positive charges (ANPC) respectively. The AHTs are found to be insensitive to stress time and temperature; the CPCs can saturate at longer stress time and higher stress temperatures; while the ANPCs do not saturate. The CPC density peak is found to be at Ef- Ev ~ 1 eV, in quantitative agreement with published measurements from Hf-based p-MOSFET. The fin width is found to have observable effect on the location of the PC density peak along the energy range, hence robust optimization of the fin width is crucial for better immunity against NBTI.

The effect of gate oxide thickness and drain bias on NBTI degradation in 45nm PMOS

This paper presents the effects of gate oxide scaling and drain bias variation on the Negative Bias Temperature Instabilities (NBTI) of a 45nm PMOSFET. The gate oxide thickness parameter is varied in this work at values of 1.8nm, 2nm and 3nm. The drain bias of the PMOS is also varied, at values 50mV and 1.2V, in order to observe its effect on the NBTI of the PMOS. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At decreasing gate oxide thickness, the PMOS transistor presents a higher interface trap concentration but exhibits improvement in the threshold voltage shift and less degradation in the drain current, when a high stress temperature and large negative bias are applied. In addition to that, the stressed transistor would exhibit significant current degradation at a higher drain bias.

Effect of oxide thickness on 32nm Pmosfet reliability

Negative Bias Temperature Instability (NBTI) has become one of the critical reliability concerns as scaling down CMOS technology especially on the pMOSFET device. A simulation study had been conducted on 32 nm conventional pMOSFET using the technology CAD (TCAD) Sentaurus Synopsys simulator tool. In this paper, the effects of the gate oxide thickness together with drain bias variations on the NBTI are studied. The effect on the device parameters such as interface traps concentration (Nit), threshold voltage (Vth) and drain current (Id) degradation had been investigated and explained in detail.

Impacts of fin width scaling on the electrical characteristics of 10-nm FinFET at different metal gate work function

This paper investigates the effects of top fin width scaling (Wtop = 4, 6, 8 nm) of p-and n-type 10-nm FinFET on the electrical performance of the device, specifically optimized for low performance (LP) and high performance (Hp) devices. The work also studies the correlation of the metal work function to the device performance. It is observed that the transfer characteristics shown increased drain current in linear region towards increased Wtop for both p- and n-FinFET. The threshold voltage is shifted to the right for p-FinFET as the work function is increased. Oppositely for n-FinFET, they shifted to the left as the work function reduced. The Ion/Ioff ratio reduced as width increase. The observations on Ion/Ioff ratio for low performance device show the magnitude drops to 63% and 82% in n-FinFET and p-FinFET, respectively when the fin width is changed from 4 nm to 8 nm.

Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET

A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time needed for the device to achieve 10% degradation of Vth. The effect on NBTI degradation is shown to be reliant on stress conditions (stress voltage, temperature) and device architecture (gate dimensions, gate oxide thickness). The NBTI lifetime was predicted by extrapolating lifetime to the nominal operating voltage from Time-to-Fail versus stress bias and oxide electric field plots. Both plots show that the lifetime of degradation parameter of Vth is lower compared to the lifetime of degradation parameter of Idsat.

Effect of gate length on Negative Bias Temperature Instability of 32nm advanced technology HKMG PMOSFET

Negative Bias Temperature Instability (NBTI) has become a key reliability concern in semiconductor industries as devices are scaled down. A simulation study had been done on 32 nm technology node PMOS using Synopsys TCAD Sentaurus simulator tool. This paper presents the effect of gate length on NBTI of 32 nm advanced technology high-k metal gate (HKMG) PMOSFET. The effect on the device parameters such as threshold voltage (Vth), drain current (Id) and the lifetime of the device had been studied and discussed in detail. It is found that NBTI is not highly dependent on gate length at low oxide field (Eox) while at higher Eox, longer gate length is shown to significantly affect the Vth degradation where Vth degradation in longer gate length is found to be lowered by 23.39% compared to the shorter.

Optimization of MEMS intraocular capacitive pressure sensor

MEMS intraocular capacitive pressure sensor is used for monitoring glaucoma disease. The structure of the diaphragm of MEMS capacitive pressure sensor is one of the important factors which could affect the sensors performance. In this paper, Taguchi and Two-Level Factorial approach are employed to optimize the size of diaphragm thickness, slot width, and slot length. The typical range of intraocular pressure is at 0 - 60 mmHg and applied on 550 × 550 μm four slotted diaphragms. The effects of sensitivity and linearity on these parameters are investigated. From this study, it is found that the optimized parameters are 4.2μm, 25μm, and 100μm for diaphragm thickness, slot width, and slot length respectively. Simulated results by COMSOL Multiphysics indicate that the optimized parameters produce more sensitivity with high linearity compared to the initial parameters condition.