N. Garry Tarr

Passive broadband silicon-on-insulator polarization splitter

We present the implementation of a novel wavelength independent polarization splitter on a silicon-on-insulator platform. The waveguide splitter is based on a zero-order arrayed waveguide grating (AWG) configuration. The splitting function is realized by employing cladding stress-induced birefringence. The device demonstrated a TE to TM splitting ratio better than -15 dB over a 20 nm tuning range centered around lambda=1550 nm and better than -10 dB over our entire accessible wavelength range from lambda=1465 nm to 1580 nm. The highest splitting extinction ratio achieved was -20 dB. To our knowledge, this is the first reported passive broadband polarization splitter based on AWG.

Stress-induced birefringence in silicon-on-insulator (SOI) waveguides

We show that stress engineering can be used to adjust the SOI waveguide birefringence to the stringent polarization tolerances expected of commercial devices, using only standard silicon processes. With decreasing device dimensions and high index contrast the waveguide birefringence becomes increasingly sensitive to device geometry. As a result, it is almost impossible to eliminate waveguide birefringence by adjusting waveguide profile alone. This paper presents, for the first time, a systematic study of the stress-induced birefringence of SOI waveguides. Through full-vectorial finite-element simulations, we investigate the variation of stress-induced birefringence with waveguide core and cladding geometries. It is found that the stress-induced birefringence is determined by the waveguide cross-section, the upper cladding layer thickness, and film stress levels. We develop a waveguide model that predicts the total waveguide birefringence and guides the post-fabrication processing steps. An experimental demonstration of a polarization insensitive SOI arrayed waveguide grating (AWG) demultiplexer is presented. The polarization dependent wavelength shifts measured experimentally agree well with the simulations.

Schottky photodetector integration on LOCOS-defined SOI waveguides

Ni/nSi and Pt/nSi Schottky barrier diodes have been integrated with SOI optical waveguides produced using the Local Oxidation of Silicon (LOCOS) technique. The smooth, nearly planar topography provided by LOCOS allows the Schottky metal to overlap the waveguide rib while still giving low leakage current densities (<10-5 Acm-2 for Ni and <10-7 Acm-2 for Pt at 1 V reverse bias). Correcting for input coupling loss, responsivities of 4.7 mA/W and 4 μA/W were obtained for 500 μm long Ni and Pt diodes respectively at 1310 nm. At 1550 nm the responsivity for Ni was 1.8 mA/W while Pt did not give a measureable response.

Athermal and low loss ridge silicon waveguides

In this paper, we investigate athermal and low propagation loss silicon-on-insulator (SOI) rib waveguides. Propagation losses have been modeled for different dimensions of ridge waveguides achieving good agreement with experimental measurements. At certain waveguide widths, it is possible to obtain low propagation losses for both TE (transverse electric) and TM (transverse magnetic) modes. Racetrack ring resonator structures based on ridge waveguides covered by a polymer have been fabricated, aiming for an athermal design and therefore, a very small temperature dependent wavelength shift. Design guidelines for temperature insensitive and small propagation loss ridge waveguides are presented in this paper together with experimental data.

Coplanar waveguides in silicon with low attenuation and slow wave reduction

This paper presents coplanar waveguide structures with low attenuation and slow-wave reduction implemented in standard silicon technologies and suitable for frequencies of up to 40 GHz. Optimization and modelling of slow-wave coplanar waveguides (SW-CPW) is provided here and compared to standard CPW models. An on-chip SW-CPW attenuation of 0.25 dB/mm at 40 GHz is obtained, compared with 2.8 dB/mm for a standard CPW. As an application, a non-linear transmission line (NLTL) was designed using SW-CPW sections. This NLTL can sharpen the pulse rise time by 75%. This work demonstrates the feasibility and advantage of using SW-CPW techniques to build all-silicon pulse-compression NLTLs using commercial silicon foundry processes.

A CMOS-compatible rib waveguide with local oxidation of silicon isolation

The Local Oxidation of Silicon (LOCOS) technique is used to define optical rib waveguides in silicon-on-insulator (SOI) material. This process, commonly used for device isolation in purely microelectronic CMOS processes, results in a nearly planar surface suitable for integrating optical and electronic components on the same chip. Optical mode simulation was used to determine rib geometries suitable for single-mode propagation and minimizing birefringence in the 1550 nm optical telecommunications band. Test devices were then fabricated in SOI material with a Si film thickness near 3 microns. Growth of a 1 micron field oxide by wet oxidation yielded a 0.5 micron rib height. As-drawn rib widths ranged from 3 microns to 5 microns, giving final rib widths ranging from 2 microns to 4 microns after oxidation. Cutback optical testing of 3 microns drawn width ribs showed the loss to be less than 1 dB/cm at 1555 nm. Unbalanced Mach-Zehnder interferometers with Y-splitter junctions were also fabricated and tested with input wavelength swept from 1470 to 1580 nm and showed an extinction of 6-10 dB, demonstrating the ability of the LOCOS rib technique to produce more complex waveguide devices.

Fabrication and modelling of screen-printed active electrolytic polymer devices

Active polymer materials allow the construction of cheap, flexible circuitry using simple printing techniques. A process and devices capable of performing a variety of circuit functions using electrolytic technology have been developed. The process is based on a simple screen printing system that allows the formation of multilayer circuitry with no active layer-to-layer alignment. Using this system, it has been possible to build a number of circuits utilizing transistor-like electrolytic devices and other active devices with novel topologies. Models have been developed that provide the ability to simulate arbitrary device geometries using a standard-cell approach for the basic elements required. These have allowed accurate simulation of the dynamic response of a number of device structures to be performed.

Perforated Mach-Zehnder interferometer evanescent field sensor in silicon-on-insulator

This paper investigates an evanescent field refractive index sensor based on a planar waveguide silicon-on-insulator (SOI) unbalanced Mach-Zehnder interferometer structure. The key element used for enhancing the sensitivity of the device is a waveguide structure that contains perforations through its core guiding layer. Three-dimensional numerical solution of the wave equation was used to determine optimal device dimensions and model device behavior. Devices were then fabricated in 3.4 μm thick SOI material and optically characterized. It was found that the perforations in the waveguide increased its sensitivity to refractive index changes in the cladding by a factor of two. The sensitivity of the device, which contained a 100 μm long sensing region, was estimated to be 2.2 nm shift in the interferometer output spectrum per unit refractive index change of the cladding. It is expected that further optimization of the perforated waveguide structure will result in a significant increase in sensitivity.

Optical image sensors and their application in radon detection

This paper reports on the development and testing of a direct reading radon detector assembled from consumer electronics at very low cost. An electrostatic concentrator constructed by metalizing a plastic funnel is used to focus charged radon progeny onto the exposed surface of an optical image sensor from a webcam. Alpha particles emitted by the collected progeny strike the image sensor, generating sufficient charge to completely saturate one or more pixels The high voltage required by the concentrator is generated using a simple Cockcroft-Walton charge pump. A personal computer is used to analyze the webcam data. Alpha particles were counted at a rate of 5.2 counts/ hour at a radon concentration of 159 Bq/ m3.

Deep submicron LOCOS-defined SOI photonic wire waveguides

The LOCOS technique for formation of SOI optical waveguides has been extended to produce low-loss photonic wire channel waveguides with deep submicron dimensions using a very simple process.