Rony E. Amaya

A 27 GHz fully integrated CMOS distributed amplifier using coplanar waveguides

This paper reports a CMOS distributed amplifier which operates from 1-27 GHz. This amplifier exhibits a measured gain of 6 dB and uses coplanar waveguides to implement required inductances. Power consumption is 68.1 mW while driven from a 3.3V supply but it can operate with supply voltages as low as 1.8V. Chip area is 1.8 /spl times/ 0.9 mm. To the authors knowledge this is the fastest frequency of operation ever reported for a distributed amplifier implemented in a standard CMOS technology.

High-Performance, Compact Quasi-Elliptic Band Pass Filters for V-Band High Data Rate Radios

This paper presents a comparison of the design and implementation of V-band quasi-elliptic band pass filters suitable for system-on-package integration at millimetre-wave frequencies. Filters were designed and manufactured at low-temperature co-fired ceramic (LTCC) and alumina substrates. Filter circuits include the input/output coplanar waveguide to microstrip transitions as well as the microwave pads, used to facilitate measurement. Three four-pole filters incorporating half-wavelength resonators were implemented, two planar (on LTCC and alumina substrates) and one vertically stacked (on LTCC). In addition a six-pole filter was also implemented in alumina. The four-pole LTCC based filters have a measured insertion loss (IL) as low as 3.4 dB, fractional bandwidth (FBW(%) = BW-3 dB/Center Frequency) of 4.8% and return loss better than 10 dB. Total filter size is less than 1.1 × 0.74 mm. The alumina-based four-pole/six-pole filters exhibit a measured IL of 2.8/3.1 dB, FBW of 8.3%/12.6%, respectively. Both alumina filters exhibit a return loss better than 10 dB and with a corresponding filter layout footprint of less than 1.01 × 1.34 mm. A new figure-of-merit (HPFOM) is proposed and results from the filters proposed here clearly show they offer the best trade-off between performance and area (higher HPFOM).

1 W, Highly Efficient, Ultra-Broadband Non-Uniform Distributed Power Amplifier in GaN

This letter describes the design and implementation of a highly linear, ultra-broadband non-uniform asymmetric distributed MMIC power amplifier in GaN, delivering 1 W of output power and suitable for operation at frequencies up to 6.5 GHz. The GaN HFETs used here have a gate length of 500 nm, and breakdown-voltages exceeding 100 V while exhibiting an fT of approximately 30 GHz. A non-uniform asymmetric distributed topology is used to achieve ultra-broadband performance. CW measurements carried out at nominal bias between 0.5 GHz and 6.5 GHz yielded a maximum PAE of 38.1% at 0.5 GHz, with PAE higher than 20% over the entire band, while achieving Pout > 30 dBm.

A novel compact three-dimensional CMOS branch-line coupler using the meandering ECPW, TFMS, and buried micro coaxial technologies at 60 GHz

This paper proposes a new approach for realizing a compact 3-D 90° hybrid coupler incorporating compact meandered elevated coplanar waveguides (ECPW), thin-film microstrip (TFMS) transmission lines, and micro coaxial shunt stub loading. The design technique has been successfully demonstrated using a multi-layer 90nm CMOS process. The proposed coupler takes advantage of the multi-level metallization processes offered in CMOS technology. The intrinsic area of the fabricated 3-D hybrid coupler is significantly reduced with a size reduction of 81% in circuit area at 60 GHz as compared to that of a conventional hybrid coupler using the ECPW/TFMS configuration. Simulated and experimental results are presented in support of the novel miniature coupler.

Analysis and measurements of EM and substrate coupling effects in common RF integrated circuits

An investigation of coupling between inductors and resonators fabricated in Si substrates is presented and the effects on RF systems and components is discussed. EM simulators (e.g., Agilent Momentum) provide accurate near field analysis of coupling in lossy and complex silicon substrates. Measurements verify theory and a novel experimental technique to measure inductor and resonator coupling makes use of injection-lockable bipolar oscillators. The experiment is fast, accurate, and unique in that no matching, probe de-embedding, or calibration is necessary as the ratio of two on-chip signals is measured to yield the results. As an example, accounting for inductor coupling in a 4.7 GHz LNA reduces the amplifiers gain from 22 dB to 18 dB.

Design of mM-W Fully Integrated CMOS Standing-Wave VCOs Using Low-Loss CPW Resonators

The design of two fully integrated 43-GHz voltage-controlled oscillators (VCOs) implemented in a 90-nm CMOS process is presented. Both use standing-wave transmission line resonators instead of a lumped tank to provide extended output frequency ranges and relatively low phase noise (PN). Coplanar waveguide structures with and without slow-wave features were employed in the two VCO circuits. The test results of the manufactured chips were compared. The circuit with the slow-wave feature showed a lower PN (-102.7 dBc/Hz at 1 MHz), whereas the one without the slow-wave structure showed a wider tuning range (1.96 GHz). The two VCOs were developed for use in licensed E-band transceiver systems.

Adapting the Doherty amplifier for millimetre-wave CMOS applications

This paper investigates the difficulties of implementing a Doherty power amplifier (DPA) in CMOS at millimetre-wave (mm-wave) frequencies. A simplified circuit-level model of the Doherty is proposed to study the performance limitations of deep sub-micron technologies, namely the output impedance, knee voltage, and breakdown voltage. Subsequently, the trends found with the model are used to implement a reconfigurable DPA at E-band frequencies in a commercially available 90-nm RF-CMOS process. The DPA consumes 21.7 mA from 1.5 V and produces 11.7 dBm of output power at P1dB with a P AE of 30.6 % and a 6-dB back-off PAE of 15.6 %. The reconfigurable option is bias controlled and improves the gain by 3.2 dB while increasing the current consumption by 7.1 mA. The circuit footprint is 1.53 mm2 and the efficiency characteristics are within 5 % of the model prediction.

A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler

This paper presents the design and realization of a downconversion mixer fabricated in a standard 130nm commercial CMOS process and aimed at applications in the 60 GHz ISM band. A balanced mixer configuration was implemented using a layout efficient 90° hybrid coupler which serves as a diplexer to inject the LO signal while also providing two outputs with 3dB of attenuation and 90° phase shift. The mixer achieves a conversion gain of +0.3 dB and an OIP3 of +2.3 dBm. The mixer also consumes 200µA of DC current and 8mA of peak current while driven from a single 2V supply. The layout area, including test pads, is 1.4mm × 1.0mm.

Coplanar waveguides in silicon with low attenuation and slow wave reduction

This paper presents coplanar waveguide structures with low attenuation and slow-wave reduction implemented in standard silicon technologies and suitable for frequencies of up to 40 GHz. Optimization and modelling of slow-wave coplanar waveguides (SW-CPW) is provided here and compared to standard CPW models. An on-chip SW-CPW attenuation of 0.25 dB/mm at 40 GHz is obtained, compared with 2.8 dB/mm for a standard CPW. As an application, a non-linear transmission line (NLTL) was designed using SW-CPW sections. This NLTL can sharpen the pulse rise time by 75%. This work demonstrates the feasibility and advantage of using SW-CPW techniques to build all-silicon pulse-compression NLTLs using commercial silicon foundry processes.

Gain bandwidth considerations in fully integrated distributed amplifiers implemented in silicon

A study of the gain and bandwidth limitations of a distributed amplifier implemented in silicon substrates is presented. It was found that the gain bandwidth product is limited to approximately 55% of the f/sub max/ of the gain stage used. This study considered three commonly used gain stages in a distributed amplifier: single device, cascode and Darlington f/sub T/ doubler. A limit on the bandwidth for the distributed amplifier is presented as a function of the choice of gain cell, quality of the passives, and the number of stages used. Gain and matching considerations are also presented. Measurements of three distributed amplifiers verify the simulation results.