N. Ketteniss

Recessed-Gate Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistors on Si with Record DC Performance

Enhancement-mode devices are in the centre of current research on group-III nitride transistors. The realisation of high-performance enhancement-mode transistors via gate recessing requires damage-free processing. We report on enhancement-mode AlGaN/GaN-on-Si heterostructure field-effect transistors (HFETs) fabricated with a damage-free digital etch technique. The threshold voltage (Vth) achieved is as high as +0.5 V. For AlGaN/GaN-on-Si HFETs, a record extrinsic transconductance (gm) of 420 mS/mm and a record maximum drain current Idmax of 500 mA/mm have been demonstrated. Furthermore, proper turn-off characteristics have been realised. Pulsed I–V characteristics reveal nearly no current collapse.

Study on quaternary AlInGaN/GaN HFETs grown on sapphire substrates

We report on AlInGaN/GaN heterostructure field effect transistors (HFETs) and the effect of different barrier material compositions. The analytical model for the interface charge in quaternary nitride heterostructures is described in detail and is applied in the calculation of the expected sheet carrier density. Experimental results from different lattice-matched AlInGaN/GaN heterostructures are presented and compared with the analytical predictions. Three heterostructures with AlInGaN barriers grown on sapphire substrates were processed and have been investigated. Each barrier layer was lattice-matched to GaN and the gallium content was 0.1, 0.15 and 0.2 at a barrier thickness of 13.5, 12.8 and 11.3 nm, respectively. Additionally, from these experiments, the basic trends for quaternary nitride Schottky barrier contacts are discussed. Finally, comprehensive dc characterizations have been performed. All devices had a gate length of 1 µm and exhibited a good transconductance of around 260 mS mm−1 at nearly the same current density level. An increase in threshold voltage as well as a decrease in gate leakage current for increasing GaN content has been observed. The nearly constant electron mobility in the range of 1700 cm2 V−1 s−1 at room temperature is within the best reported so far for HFETs with InN-containing barriers.

First polarization-engineered compressively strained AlInGaN barrier enhancement-mode MISHFET

One current focus of research is the realization of GaN-based enhancement-mode devices. A novel approach for the realization of enhancement-mode behaviour is the utilization of polarization matching between the barrier and the GaN buffer. Yet, the utilization of a quaternary barrier combining polarization engineering together with a large conduction band offset has not been demonstrated so far. Here, epitaxially grown, compressively strained AlInGaN is applied as a nearly polarization-matched barrier layer on GaN resulting in enhancement-mode operation. The insulated-gate devices are fabricated gate-first with Al2O3 as gate dielectric. Passivated metal insulator semiconductor heterostructure field effect transistors yielded threshold voltages (Vth) of up to +1 V. The devices withstand negative and positive gate-biased stress and a positive Vth is maintained even after long-time negative bias stress.

InAlN/GaN HEMTs on Sapphire Substrate With 2.9-W/mm Output Power Density at 18 GHz

In this letter, small- and large-signal measurements of an In_0.15Al_0.82N/AlN/GaN high-electron-mobility transistor (HEMT) grown on a sapphire substrate with a 225-nm T-shaped gate are described. A maximum dc current density of 1.2 A/mm and a peak extrinsic transconductance of 460 mS/mm are obtained. The device exhibits a current gain cutoff frequency (<i>F</i>_T) and a power gain cutoff frequency (<i>F</i>_MAX) of 52 and 120 GHz, respectively. At <i>V</i>_DS = 15 V, a continuous-wave output power density of 2.9 W/mm was achieved at 18 GHz with an associated power-added efficiency of 28% and a power gain of 15 dB. It is the best value ever reported from InAlN/GaN HEMTs grown on a sapphire substrate.

Electrical properties of thermally oxidized AlInN/AlN/GaN-based metal oxide semiconductor hetero field effect transistors

In this work, we report on the thermal oxidation of AlInN/AlN/GaN heterostructures. A “nearly native” Al2O3 oxide was formed during this oxidation procedure, which can be used as a gate oxide and thus enables the fabrication of metal insulator semiconductor hetero field effect transistors. A constant barrier height of ΦB ≈ 2.34 eV was obtained for all oxidized samples, independent of the oxidation time and temperature, indicating a stable AlInN-oxide interface. The interface state density was approximated to be as low as Nint = 2.5 × 1012 cm-2. Oxide thicknesses were estimated to be in the range of 0.6 nm and 3.2 nm, resulting in a suppression of reverse leakage currents oflarge area metal insulator semiconductor diodes by up to three orders of magnitude. Two-dimensional electron gas density and, in particular, carrier mobility are strongly affected by the thermal oxidation in the O2 atmosphere. A narrow processing window for successful thermal oxidation was identified, covering temperatures between 700 °...

Polarization-reduced quaternary InAlGaN/GaN HFET and MISHFET devices

The reduction of the polarization charge in a GaN-based single-heterostructure field-effect transistor (HFET) by polarization engineering is proposed as a method for achieving normally off operation. The concept minimizes the dependence of the threshold voltage on the barrier layer thickness. Therefore, thicker gate dielectrics for suppression of gate leakage currents can be applied without a shift in threshold voltage. A polarization-reduced enhancement-mode (E-mode) InAlGaN/GaN HFET is presented and demonstrates the basic working principle. Also an insulated-gate device with only minor shift in threshold voltage compared to the HFET validates the new concept and demonstrates the advantages compared to commonly applied concepts for E-mode operation.

Power Performance at 40 GHz on Quaternary Barrier InAlGaN/GaN HEMT

Depletion-mode high-electron mobility transistors (HEMTs) based on a quaternary barrier In0.11Al0.72Ga0.17N/GaN heterostructure on sapphire substrate are fabricated and characterized. This structure shows a very high Hall electron mobility of 2200 cm2/V·s, which is the highest value ever reported on In-containing GaN-based HEMTs. For T-shaped gate transistor with a gate length of 75 nm, current gain (ft) and power gain (fmax) cutoff frequencies of 113 and 200 GHz are extracted from S-parameter measurements, respectively. Nonlinear characterization of a T-shaped gate device with a gate length of 225 nm gives an output power density of 2 W/mm at 40 GHz. These results clearly demonstrate the capabilities of such quaternary barrier-based devices.

Quaternary nitride enhancement mode HFET with 260 mS/mm and a threshold voltage of +0.5 V

A new approach for the heterostructure design following the idea to reduce the interface charge itself by applying a quaternary barrier layer with rather low polarization is demonstrated. The enhancement mode (e-mode) heterostructure field effect transistors (HFET) is consist of a GaN buffer and a quarternary barrier layers, whose composition and thickness are chosen carefully to result in an e-mode device. The devices is passivated with 120 nm SiN by plasma enhanced CVD. An increase in gate and drain leakage can be observed and finds its origin in surface or interface conductivity of the not fully optimized SiN. Nevertheless, for all devices the extrinsic transconductance has increased due to further carrier concentration enhancement in the access region by the passivation, and the best performance is achieved with maximum extrinsic transconductance of 260 mS/mm, which is among the highest reported for a 1 11m gate length e-mode HFET.

Quaternary Enhancement-Mode HFET With In Situ SiN Passivation

A lattice-matched InAlGaN/GaN heterostructure with a barrier-layer thickness of 4 nm has been grown and passivated in situ with a 63-nm SiN by metal-organic chemical vapor deposition. Enhancement-mode heterostructure field-effect transistors have been realized by a fluorine-based surface treatment after the local removal of the SiN. The threshold voltage and transconductance were 0.65 V and 250 mS/mm, respectively, for a 1-μm gate-length device. The benefits of an in situ SiN passivation are demonstrated: first, the stabilization of the barrier material and prevention from oxidation and second, the improvement of the device characteristics by reduced source resistance and reduced trapping effects.

Influence of mask material and process parameters on etch angle in a chlorine-based GaN dry etch

The vertical structuring of GaN layers for power application purposes is a key step for successful device operation. Thus, the dry etching of GaN becomes a crucial step. While etch rates and surface roughness have been analyzed well, the sidewall angle of the etched GaN has drawn less attention. In this paper, the authors report on the influence of mask material and etch parameters in an inductively coupled plasma reactive ion etching process on the angle of the etched GaN sidewall. Deep etches up to 3.3 μm are shown. The authors show how the sidewall angle can either be adjusted to high values up to 80° or, if necessary, to small angles down to 46°.