N. V. D'Halleweyn
University of Southampton
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Publication
Featured researches published by N. V. D'Halleweyn.
IEEE Transactions on Electron Devices | 2001
J. Benson; N. V. D'Halleweyn; W. Redman-White; Craig A. Easson; Michael J. Uren; O. Faynot; Jean-Luc Pelloie
Compact MOS models based on surface potential are now firmly established, but for practical applications there is no reliable link between measured values of threshold voltage and the flat-band voltage on which such models are based. This brief presents an analytical relationship which may be implemented in compact models to provide a reliable and accurate threshold parameter input. Results are compared with a conventional threshold voltage model for several SOI CMOS technologies. This technique has been developed for use with body-tied SOI transistors, and hence it can also be applied to bulk devices.
international symposium on power semiconductor devices and ic s | 2001
N. V. D'Halleweyn; L.F. Tiemeijer; J. Benson; W. Redman-White
In this paper we present a compact physically based charge model, which describes accurately the unique features of the SOI LDMOS. The model uses a modified Ward and Dutton partitioning scheme to account for the lateral doping gradient in the channel region and the overlap of the front gate over the drift region. The model has been implemented in SPICE3f5 and capacitance measurements are shown to agree well with the simulations.
radio frequency integrated circuits symposium | 2003
K. Mistry; W. Redman-White; J. Benson; N. V. D'Halleweyn
This work describes a high frequency dual modulus divider designed and fabricated in a 0.35 /spl mu/m PDSOI process, employing a stacked topology phase switching scheme. SOI CMOS technology is exploited to allow current re-use in a higher supply voltage than dictated by single device breakdown. Measurements show the circuit operating at 3GHz (Vdd = 6.8V.).
Solid-state Electronics | 2002
J. Benson; W. Redman-White; N. V. D'Halleweyn; Craig A. Easson; M.J. Uren
Abstract We show that careful modelling of body node elements in floating body PD-SOI MOSFET compact models is required in order to obtain accurate small-signal simulation results in the saturation region. The body network modifies the saturation output conductance of the device via the body–source transconductance, resulting in a pole/zero pair being introduced in the conductance–frequency response. We show that neglecting the presence of body charge in the saturation region can often yield inaccurate values for the body capacitances, which in turn can adversely affect the modelling of the output conductance above the pole/zero frequency. We conclude that the underlying cause of this problem is the use of separate models for the intrinsic and extrinsic capacitances. Finally, we present a simple saturation body charge model which can greatly improve small-signal simulation accuracy for floating body devices.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2004
N. V. D'Halleweyn; J. Benson; W. Redman-White; Ketan Mistry; M. Swanenberg
Archive | 2001
K. Mistry; W. Redman-White; J. Benson; N. V. D'Halleweyn
Archive | 2001
N. V. D'Halleweyn; J. Benson; M. Swanenberg; W. Redman-White
Archive | 2003
J. Benson; N. V. D'Halleweyn; K. Mistry; W. Redman-White
Archive | 1999
N. V. D'Halleweyn; M. Swanenberg; James Benson; W. Redman White
Focus on Catalysts | 1999
John D. Benson; W. Redman-White; Craig A. Easson; N. V. D'Halleweyn; M.J. Uren