J. Benson

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

A physically based relation between extracted threshold voltage and surface potential flat band voltage for MOSFET compact modeling

Compact MOS models based on surface potential are now firmly established, but for practical applications there is no reliable link between measured values of threshold voltage and the flat-band voltage on which such models are based. This brief presents an analytical relationship which may be implemented in compact models to provide a reliable and accurate threshold parameter input. Results are compared with a conventional threshold voltage model for several SOI CMOS technologies. This technique has been developed for use with body-tied SOI transistors, and hence it can also be applied to bulk devices.

Charge model for SOI LDMOST with lateral doping gradient

In this paper we present a compact physically based charge model, which describes accurately the unique features of the SOI LDMOS. The model uses a modified Ward and Dutton partitioning scheme to account for the lateral doping gradient in the channel region and the overlap of the front gate over the drift region. The model has been implemented in SPICE3f5 and capacitance measurements are shown to agree well with the simulations.

A high speed dual modulus divider in SOI CMOS with stacked current steering phase selection architecture

This work describes a high frequency dual modulus divider designed and fabricated in a 0.35 /spl mu/m PDSOI process, employing a stacked topology phase switching scheme. SOI CMOS technology is exploited to allow current re-use in a higher supply voltage than dictated by single device breakdown. Measurements show the circuit operating at 3GHz (Vdd = 6.8V.).

Body Charge Modelling for Accurate Simulation of Small-Signal Behaviour in Floating Body SOI

Abstract We show that careful modelling of body node elements in floating body PD-SOI MOSFET compact models is required in order to obtain accurate small-signal simulation results in the saturation region. The body network modifies the saturation output conductance of the device via the body–source transconductance, resulting in a pole/zero pair being introduced in the conductance–frequency response. We show that neglecting the presence of body charge in the saturation region can often yield inaccurate values for the body capacitances, which in turn can adversely affect the modelling of the output conductance above the pole/zero frequency. We conclude that the underlying cause of this problem is the use of separate models for the intrinsic and extrinsic capacitances. Finally, we present a simple saturation body charge model which can greatly improve small-signal simulation accuracy for floating body devices.

Circuit simulator and compact model requisites for accurate simulation of AC floating body behaviour in PD SOI

Investigations of floating body behaviour of partially depleted (PD) SOI MOSFETs have established the presence of frequency-dependent drain conductance behaviour below the onset of the kink effect (Howes and Redman-White, 1992). This is due to capacitive coupling, and is not related to self-heating (Caviglia and Iliadis, 1992; Redman-White et al. 1992). As the conductances associated with the body node are extremely low in this region, we found that there are unexpected constraints on both the formulation of PD SOI compact models and their implementation in circuit simulation packages.