Na Bai

A Circuit for Robustness Enhancement of the Subthreshold SRAM Bitcell in 65nm Technology

This paper describes a circuit which can enhance the robustness of the subthreshold 6T SRAM bitcell. The proposed circuit can dynamically adjust the body voltages of the PMOS transistors in order to enhance the robustness of the subthreshold 6T SRAM bitcell by detecting the variation of the threshold voltage. The simulation results under 300mV in 65nm technology demonstrate that the mean values of the read and hold static noise margin (SNM) of the subthreshold 6T SRAM bitcell have been improved by 18% and 0.7%, respectively, meanwhile the standard values of the read and hold SNM have improved by 82% and 29.4%, respectively, by adopting the proposed circuit. Moreover, the proposed circuit functions well in a wide range of supply voltage from 0.2V to 0.5V.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.