Nachiket R. Raravikar

Interfacial thermal conductance between silicon and a vertical carbon nanotube

Molecular simulations are used to evaluate thermal resistance between crystalline silicon and a vertically oriented carbon nanotube (CNT). Without chemical bonds between CNT and Si the thermal resistance is high and its values are consistent with that measured in experiment on vertical CNT arrays. With chemical bonds the thermal resistance is reduced by two orders of magnitude demonstrating significant potential of CNT arrays for thermal management applications. The underlying mechanism for the very large effect of chemical bonding is revealed by simulations of individual phonon scattering across the interface and understood within an analytical solution of a simple spring-mass chain model.

Thermal energy exchange between carbon nanotube and air

Using molecular dynamics simulations the authors impose a heat flux between single-walled carbon nanotubes and air to study thermal interfacial conductance. They estimate that the nanotube-air interfacial thermal conductance is about 0.1MW∕m2K at room temperature and atmospheric pressure. The associated interfacial thermal resistance is equivalent to the resistance of 250nm thick layer of air. They also show that the interfacial resistance is a strong function of the interaction parameters between air atoms and carbon nanotubes.

Air flow through carbon nanotube arrays

Using molecular dynamics simulations, we studied the air flow through carbon nanotube arrays. We found that for 1.4nm diameter tubes separated by 25nm, the air flow can be well described by the free molecular flow theory. We estimate that for such array, the pressure gradient is about 0.1atm∕μm at 1atm air pressure and 5m∕s flow velocity, indicating that the flowing air can only pass through an array of no more than about 400 carbon nanotubes in series. Our findings provide design rules for arrays of nanotubes for thermal energy exchange with air.

Tombstone Initiation Model for Small Form-Factor Surface Mount Passives

Passive components such as capacitors are shrinking in size in electrical systems in tandem with the device transistor features. With the size shrink comes an increased risk of process-induced defects such as capacitor tombstoning or billboarding. These defects involve poor connectivity of capacitor terminations to the substrates, affecting the electrical performance of the system. We have developed an analytical model to predict the probability of such defects to occur as a function of the design and process factors. The model demonstrates that the surface tension at component terminals dominates over the inertia forces (component weight) in case of components with submilligram weight. Bulkier capacitors have lower risk of tombstoning compared to the lighter ones. The analysis also points to other modulating factors such as component termination width, component height, solder pad size, and the solder paste volume. We also present the experimental results on small form-factor components that confirm some of the predictions for the model. Optimum design guidelines for the electrical systems with soldered components can be obtained from the current model.