Neha M. Patel

High-density compliant die-package interconnects

Reduction in inter-level dielectric (ILD) constant has been accompanied by a reduction in ILD adhesive and cohesive strength thus increasing potential for under bump (flip-chip) ILD cracking during packaging and reliability testing. Two primary mechanisms were determined to cause this failure: (1) stress on the ILD created due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the package substrate; and (2) the die-to-package interconnection, i.e. the bump, transmits the CTE-induced mismatch stresses directly to the ILD (Chandran et al., 2004). Compliant die-package interconnects (Zhu et al., 2004) substituted for conventional C4 flip-chip interconnections promises to offer reduction in package induced stresses onto the silicon die consisting of low-k ILD layers. The reduction of stresses achieved with these compliant interconnects is by decoupling the die and the package substrate such that either entity is able to deform without constraining the other. Extensive thermomechanical simulation using various modeling approaches predicts an ILD stress reduction offered by compliant interconnects to be between 17-57% relative to conventional C4 flip-chip bump. A prototype compliant interconnect structure was fabricated on a low-k ILD silicon test-chip with 180mum C4 pitch and packaged onto an organic substrate with Pb-free solder. Assembly end-of-line (EOL) data was collected to assess the ILD stress reduction, warpage analysis, Imax and electromigration performance of the compliant interconnects. The focus of this paper is a comparison of the performance of compliant die-package interconnects as a substitute for conventional C4 flip-chip bump technologies in low-k ILD architectures

Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect

The EMIB dense MCP technology is a new packaging paradigm that provides localized high density interconnects between two or more die on an organic package substrate, opening up new opportunities for heterogeneous on-package integration. This paper provides an overview of EMIB architecture and package capabilities. First, EMIB is compared with other approaches for high density interconnects. Some of the inherent advantages of the technology, such as the ability to cost effectively implement high density interconnects without requiring TSVs, and the ability to support the integration of many large die in an area much greater than the typical reticle size limit are highlighted. Next, the overall EMIB architecture envelope is discussed along with its constituent building blocks, the package construction with the embedded bridge, die to package interconnect features. Next, the EMIB assembly process is described at a high level. Finally, high bandwidth signaling between the die is discussed and the link bandwidth envelope is quantified.

Characterization of Novolac Based Photoresists to Fabricate 3D Polymer Dome Features

Wafer level, 3D, free standing structures (e.g., domes or hemi-cylinders) can be fabricated using polymer dome features as sacrificial templates for MEMS and interconnect applications. Understanding the kinetics of dome formation and the material properties are essential for a robust and manufacturable process of controlling the size and shape of the photoresist features. In this paper, temporal and thermal characteristics of Novolac based photoresists are presented as a function of solid loading and solvent type using analytical techniques such as Thermogravimetric Analysis (TGA), Fourier Transform Infrared (FTIR) spectroscopy, hot stage microscopy, and Gas Chromatography/ Mass Spectrometry (GC/MS). The solid loading influences the thickness and processing ability of the resist. The solvent evaporation rate controls the final size and shape of the 3D polymer dome features. Solvent is the primary material lost during the dome formation and the onset of deformation is dependent on temperature and ramp rate.Copyright