Nader Akil

Impact of the charge transport in the conduction band on the retention of Si-nitride based memories

An improved model for charge injection through ONO gate stacks, that comprises carrier transport in the conduction band of the silicon nitride (Si3N4), is used to investigate the program/retention sequence of Si3N4 based (SONOS/TANOS) non volatile memories without making assumptions on the initial distribution of the trapped charge at the beginning of retention. We show that carrier transport in the Si3N4 layer impacts the spatial charge distribution and consequently several other aspects of the retention transient. The interpretation of the Arrehnius plots of the high temperature retention data, typically used to infer the trap depth from the retention activation energy is discussed. The model provides a simple explanation of the small threshold voltage increase observed during retention experiments of thick tunnel oxide ONO stacks.

Programme and retention characteristics of SONOS memory arrays with layered tunnel barrier

Layered tunnel barriers (T-ONO) might help circumvent retention limitations of nitride charge trapping devices (SONOS) programmed/erased by direct tunnelling without invoking high-K dielectrics in the gate stack. In order to establish to what extent the properties of a T-ONO tunnel layer influence the performance of SONOS memories, NOR memory arrays containing a silicon oxide/silicon nitride/silicon oxide T-ONO layer, a silicon nitride charge trapping layer and a silicon oxide blocking layer were fabricated and investigated. The T-ONO layer was formed using wet reoxidation of the silicon nitride, as this process is known to generate a lot of traps at the interface between silicon nitride and silicon oxide, as well as in the reoxidized portion of the silicon nitride itself. Besides standard memory measurements like programme/erase behaviour, endurance and retention, charge centroid extraction measurements were carried out in order to explain the retention behaviour and associate it with the position of the charge. It has been demonstrated that the performance of SONOS memories with a T-ONO layer strongly depends on the technological properties/quality of the T-ONO barrier which, therefore, may not be a universal solution to retention problems in SONOS devices.

A Simulation Study of the Punch-Through-Assisted Hot Hole Injection Mechanism for Nonvolatile Memory Cells

In this paper, we investigate the operating principle and the injection efficiency of the punch-through-assisted hot hole injection mechanism for programming nonvolatile memory cells by means of full-band Monte Carlo transport simulations of realistic device structures. The effects of terminal bias and cell scaling on the injection efficiency and the uniformity of charge injection along the channel are analyzed in detail.

New writing mechanism for reliable SONOS embedded memories with thick tunnel oxide

This paper describes a new low-cost non-volatile embedded memory option for sub-100 nm CMOS processes, based on the SONOS (silicon-oxide-nitride-oxide-silicon) concept. The retention issue inherent to SONOS memories was solved by increasing the thickness of the tunnel oxide from 2 nm to 4-6 nm which is sufficient for operation temperatures up to 100degC. Because of the thicker tunnel oxide, the conventional way of erasing SONOS memory cells by means of hole tunneling can not be used anymore; therefore, a new writing mechanism, punch-through assisted hot hole injection, was developed. This mechanism has a high write speed (~100 mus) at moderate voltages (absolute biases are below 5-6 V). Thanks to these low operation voltages, no dedicated high-voltage transistors are needed, thus reducing the integration costs of the memory significantly.

Low Voltage and Fast Program and Erase SONOS with Thick Tunnel Oxide for Low Cost Embedded EEPROM-like Memory Applications

We have presented a new programming scheme for thick tunnel oxide (4-6nm) SONOS memories. The programming is done with conventional CHEI while erasing is performed with PAHHI. Low voltage (|VCG|< 5V, VDs=5V) is used for program and erase. The programming scheme is favorable for short CG lengths (LCG< 100 nm) and yields good memory characteristics: 5.5V VT window (symmetric around 0V), 100mus program and erase time, endurance of 10k cycles (which demonstrates a good compatibility between CHEI and PAHHI), excellent immunity to gate and drain disturbs, and good memory retention (10 years at 100degC). The presented operation scheme enables the implementation of low cost and reliable embedded SONOS memories with a small EEPROM-like granularity in sub-100 nm CMOS generations without the need for high voltage processing.

26 kbit Two Transistor Low Voltage/Low Power NOR Charge Trapping Flash Memory with HfSiON and TiN Metal gate

In this paper, the 2T NOR CTNVM with HfSiON and TiN metal gate has been investigated using 128 bit and 26 kbit array vehicles, which are programmed/erased by direct tunnelling of electrons/holes from the Si channel. It has been demonstrated that with programme/erase (P/E) voltages as low as plusmn10 V, a threshold voltage (VT) window in excess of 4V can be achieved with 1 ms - 10 ms pluses, combined with an excellent endurance up to 10 P/E cycles and a good room temperature retention.