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Dive into the research topics where Nadia Galbiati is active.

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Featured researches published by Nadia Galbiati.


international reliability physics symposium | 2006

Oxide Thinning in Shallow Trench Isolation

G. Ghidini; Roberta Bottini; Daniela Brazzelli; Nadia Galbiati; I. Mica; Adelaide Morini; Alessia Pavan; Maria Luisa Polignano; Maria Elena Vitali

Aim of this work is to study the thinning of thick HV gate oxides in flash and embedded flash processes due to the shallow trench isolation (STI) induced stress on oxide growth


Microelectronics Reliability | 2005

Impact of interface and bulk trapped charges on transistor reliability

G. Ghidini; M. Langenbuch; Roberta Bottini; Daniela Brazzelli; Andrea Ghetti; Nadia Galbiati; G. Giusto; A. Garavaglia

Oxide reliability is a key issue and the main topic of several recent works. We study the impact of gate oxide stress on transistor performances following a methodology similar to oxide lifetime characterisation in capacitors. A universal trend for degradation of the threshold voltage and drain saturation current with injected charge is observed and the impact of boron on trapping enhancement has been separated by comparing n-MOS and p-MOS.


international reliability physics symposium | 2007

Methodology for Word Line-Contact Dielectric Characterization in Flash Normemories

G. Ghidini; Roberta Bottini; M. Brambilla; Daniela Brazzelli; Nadia Galbiati; A. Ghetti; A. Mauri; C. Scozzari; A. Sebastiani.

Aim of this work is to study the reliability of the dielectric between cell control gate and drain contact. Conduction characteristics and reliability under high field stress are investigated. The large spread in this dielectric thickness because of mask misalignment makes the usual reliability procedures very difficult to be applied. Results relative to fast and long reliability measurements are discussed, proposing a method for the evaluation of the spread between control gate and drain contact. Moreover, this methodology allows a screening of the structures with a too critical mask misalignment, or with a poor dielectric quality which could cause memory failures during cycling


Microelectronics Reliability | 2007

High voltage transistor degradation in NVM pump application

Roberta Bottini; S. Costantini; Nadia Galbiati; Andrea Ghetti; G. Ghidini; A. Mauri; C. Scozzari; A. Sebastiani

Aim of this work is to investigate the degradation of n-MOS transistor when stressed at high fields, typical operating condition when used as a pump in non-volatile memory (NVM) application. It is possible to understand where the main degradation occurs studying the degradation in different structures as a function of the stress field. Besides, the impact of different isolation processes is considered, pointing out what is the most critical issue for the degradation. Simulations of the conduction mechanism allow the fitting of the transfer characteristics of virgin transistor, while the stressed one can be described only assuming the localization of oxide positive and negative trapped charge whose amount depends on the field configuration.


Archive | 2001

Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors, with salicided junctions

Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana


Archive | 2001

Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions

Matteo Patelmo; Nadia Galbiati; Giovanna Dalla Libera; Bruno Vajana


Archive | 1999

Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors

Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana


Archive | 1999

Method for obtaining a multi-level ROM in an EEPROM process flow

Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana


Archive | 2000

Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell

Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana


Archive | 1999

Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks

Matteo Patelmo; Bruno Vajana; Giovanna Dalla Libera; Carlo Cremonesi; Nadia Galbiati

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