Nadia Galbiati
STMicroelectronics
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Publication
Featured researches published by Nadia Galbiati.
international reliability physics symposium | 2006
G. Ghidini; Roberta Bottini; Daniela Brazzelli; Nadia Galbiati; I. Mica; Adelaide Morini; Alessia Pavan; Maria Luisa Polignano; Maria Elena Vitali
Aim of this work is to study the thinning of thick HV gate oxides in flash and embedded flash processes due to the shallow trench isolation (STI) induced stress on oxide growth
Microelectronics Reliability | 2005
G. Ghidini; M. Langenbuch; Roberta Bottini; Daniela Brazzelli; Andrea Ghetti; Nadia Galbiati; G. Giusto; A. Garavaglia
Oxide reliability is a key issue and the main topic of several recent works. We study the impact of gate oxide stress on transistor performances following a methodology similar to oxide lifetime characterisation in capacitors. A universal trend for degradation of the threshold voltage and drain saturation current with injected charge is observed and the impact of boron on trapping enhancement has been separated by comparing n-MOS and p-MOS.
international reliability physics symposium | 2007
G. Ghidini; Roberta Bottini; M. Brambilla; Daniela Brazzelli; Nadia Galbiati; A. Ghetti; A. Mauri; C. Scozzari; A. Sebastiani.
Aim of this work is to study the reliability of the dielectric between cell control gate and drain contact. Conduction characteristics and reliability under high field stress are investigated. The large spread in this dielectric thickness because of mask misalignment makes the usual reliability procedures very difficult to be applied. Results relative to fast and long reliability measurements are discussed, proposing a method for the evaluation of the spread between control gate and drain contact. Moreover, this methodology allows a screening of the structures with a too critical mask misalignment, or with a poor dielectric quality which could cause memory failures during cycling
Microelectronics Reliability | 2007
Roberta Bottini; S. Costantini; Nadia Galbiati; Andrea Ghetti; G. Ghidini; A. Mauri; C. Scozzari; A. Sebastiani
Aim of this work is to investigate the degradation of n-MOS transistor when stressed at high fields, typical operating condition when used as a pump in non-volatile memory (NVM) application. It is possible to understand where the main degradation occurs studying the degradation in different structures as a function of the stress field. Besides, the impact of different isolation processes is considered, pointing out what is the most critical issue for the degradation. Simulations of the conduction mechanism allow the fitting of the transfer characteristics of virgin transistor, while the stressed one can be described only assuming the localization of oxide positive and negative trapped charge whose amount depends on the field configuration.
Archive | 2001
Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana
Archive | 2001
Matteo Patelmo; Nadia Galbiati; Giovanna Dalla Libera; Bruno Vajana
Archive | 1999
Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana
Archive | 1999
Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana
Archive | 2000
Matteo Patelmo; Giovanna Dalla Libera; Nadia Galbiati; Bruno Vajana
Archive | 1999
Matteo Patelmo; Bruno Vajana; Giovanna Dalla Libera; Carlo Cremonesi; Nadia Galbiati