Bruno Vajana

A scalable single poly EEPROM cell for embedded memory applications

An increasing number of Integrated Circuits requires the embedding of a limited amount (up to 16-64 kbits) of EEPROM memory. For this application, low process complexity, robust structure and good reliability are more important than small cell size. In this paper we present the design and characterization of a single poly EEPROM cell, optimized for embedded applications, and characterized by a good shrink potential. A cell area of 68.7¿m2 has been obtained in 0.7¿m technology, and electrical characterization has shown the possibility of achieving a programming time of less than 1 ms, while an endurance of more than 10 million cycles has been achieved at 125°C, with a programming time of 2 ms. By further shrink of the same basic layout, cell areas of 55¿m2 and 44¿m2 have been obtained, and the similar programming and endurance performances have been demonstrated.

Electrical characterization and reliability of double-doped drain MOS transistors compatible with an EEPROM process☆

Abstract Double-doped drain/source (As-P) n-MOS transistors with gate-drain and gate-source overlapping have been manufactured within a standard CMOS EEPROM process. Owing to a decrease in the longitudinal electric field, and the enhanced control of the gate on the low doped drain region, both snap-back voltage and hot electron effects are markedly reduced, allowing reliable operation at high drain voltages at the expense of a tolerable increase in drain, source/gate capacitances. Devices have been submitted to a hot electron accelerated test at V ds = 10 V , V gs = 5 V . The observed degradation seems to be mainly due to acceptor-type interface state creation near the drain junction.