Roberta Bottini

In situ steam generation (ISSG) versus standard steam technology: impact on oxide reliability

This work studies the reliability behaviour of gate oxides grown by in situ steam generation technology. A comparison with standard steam oxides is performed, investigating interface and bulk properties. A reduced conduction at low fields and an improved reliability is found for ISSG oxide. The initial lower bulk trapping, but with similar degradation rate with respect to standard oxides, explains the improved reliability results.

Oxide Thinning in Shallow Trench Isolation

Aim of this work is to study the thinning of thick HV gate oxides in flash and embedded flash processes due to the shallow trench isolation (STI) induced stress on oxide growth

Impact of interface and bulk trapped charges on transistor reliability

Oxide reliability is a key issue and the main topic of several recent works. We study the impact of gate oxide stress on transistor performances following a methodology similar to oxide lifetime characterisation in capacitors. A universal trend for degradation of the threshold voltage and drain saturation current with injected charge is observed and the impact of boron on trapping enhancement has been separated by comparing n-MOS and p-MOS.

Methodology for Word Line-Contact Dielectric Characterization in Flash Normemories

Aim of this work is to study the reliability of the dielectric between cell control gate and drain contact. Conduction characteristics and reliability under high field stress are investigated. The large spread in this dielectric thickness because of mask misalignment makes the usual reliability procedures very difficult to be applied. Results relative to fast and long reliability measurements are discussed, proposing a method for the evaluation of the spread between control gate and drain contact. Moreover, this methodology allows a screening of the structures with a too critical mask misalignment, or with a poor dielectric quality which could cause memory failures during cycling

High voltage transistor degradation in NVM pump application

Aim of this work is to investigate the degradation of n-MOS transistor when stressed at high fields, typical operating condition when used as a pump in non-volatile memory (NVM) application. It is possible to understand where the main degradation occurs studying the degradation in different structures as a function of the stress field. Besides, the impact of different isolation processes is considered, pointing out what is the most critical issue for the degradation. Simulations of the conduction mechanism allow the fitting of the transfer characteristics of virgin transistor, while the stressed one can be described only assuming the localization of oxide positive and negative trapped charge whose amount depends on the field configuration.

MOS gate current characteristics and their implications for lifetime area scaling

In this paper, the gate current in p-MOS and n-MOS devices in inversion and accumulation mode is studied. We find that in accumulation mode the current passing the oxide is not uniformly distributed over the oxide area, but much higher in the region near source and drain of the transistor. This spatially changing current density has important implications for the area scaling of the lifetime of the device. Our results for the time to breakdown show that standard (Poisson model) area scaling leads to an over-optimistic prediction for device lifetimes.